Abstract: Double data rate (DDR) synchronous dynamic random access memory (SDRAM) data is sampled into a synchronization circuit on both rising and falling edges of a data strobe (DQS) signal, into separate latches. A delay calculation and timing synchronization unit determines the location of the data strobe signal relative to rising/falling edges of an internal clock, then decides which sample to transfer into the internal data path and whether to use the rising or falling internal clock edge. Every DDR-SDRAM read transaction is thus automatically synchronized without the need for predetermined delay(s), allowing a wide range of operating frequencies and frequency variations to be accommodated.