Abstract: A power up clear (PUC) signal is generated, based on a value of a supply voltage VCC. A first circuit element (such as an n-channel MOSFET MN0) of a first conductivity type having a first characteristic threshold voltage, and a second circuit element (such as p-channel MOSFET MP0) of a second conductivity type having a second characteristic threshold voltage, are provided in a PUC signal generating circuit. A first circuit portion (including MN0, R0) is configured to provide a first comparison input signal VIN?, and a second circuit portion (including MP0, R1, R2, and, switchably, R3) is configured to provide a second comparison input signal VIN+. A comparator COMP compares the first and second comparison input signals VIN?, VIN+, to cause the PUC signal to transition to an active state when one of the first and second comparison signals crosses another of the first and second comparison signals, in response to an increasing magnitude of the supply voltage during power up.

Abstract: A clamp for a FET switch utilizes a surge detector to turn off one of two bias circuits for the FET. The first biasing circuit provides the current necessary for high speed switching. The second biasing circuit provides a lower biasing current. A resistor or other device is used to allow the measurement of BVdss on the integrated circuit where the surge detector is connected from a terminal of the conductive path of the FET to the gate thereof. The switching circuit allows the surge detector to turn on the FET to act as a self-clamp when there is a spike in the voltage applied to the FET, such as when turning off an inductive load.

Abstract: A FET switching transistor for the solenoid coil of an ABS braking system can switched ON or OFF in no more than substantially 250 ns. A higher current biasing circuit for fast turn on of the FET switching transistor is disconnected when it is necessary to limit the current flowing therethrough, whether during the inrush current to the solenoid coil or due to a fault in the system. The high speed switching of the FET switching transistor causes ringing of the current through the transistor which causes the current detector circuit to exit the current control mode. A deglitch circuit prevents the current detector from exiting the current control mode, so that a timer can be used to turn off the FET switching transistor before it can be damaged by the heat generated during current limit operation.

Abstract: An integrated circuit (10) having at least one programmable fuse (F1) and ESD circuitry (MN3, MN1) preventing the fuse (F1) from being unintentionally blown when a voltage transient exists on a main voltage potential (Vmain). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MNmain) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F1. The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.