Abstract: An oversampling delay is provided between clock and data signals by steering a current between first and second nodes. The first node is coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator. The second node is coupled to an input differential pair of the data interpolator and a delayed differential pair of the clock interpolator. First clock and data signals are provided to a first data sampling element and, respectively, to the clock and data interpolators. Second clock and data signals, respectively output from the clock and data interpolators, are provided to a second data sampling element. Additional data sampling elements may be linked to form a longer chain of data sampling elements.

Abstract: Modular, jitter-tolerant, data acquisition and processing systems are disclosed. An exemplary embodiment comprises a receiving portion having a first module configured to receive a serial bit stream and recover a serial data stream and a first clocking signal from the serial bit stream. The receiving portion also comprises a second module configured to receive the serial data stream and the first clocking signal and generate a parallel data stream and a second clocking signal.