Abstract: Refresh signals for a multiple semiconductor MOS bank memory are implemented with a refresh counter that supplies 15.6 microseconds refresh pulses so that one row of 128 row of memory bank, or of each of a group of memory banks, may be refreshed on a sequential, stepped-through basis. The occurrence of each refresh pulse is effective to refresh one row or a group of rows, providing that refresh lock-out logic does not prevent the refresh pulses signals from being applied to the memory banks. An up/down counter is initially filled to a count of eight, and counts toward zero once each time a refresh pulse occurs and the memory is busy. As long as the count has not reached zero the lock-out logic is effective, but when a count of zero occurs refresh of each new row in the sequence occurs at the 15.6 microsecond rate until the memory is no longer busy; at which time a burst of eight count up pulses is supplied to the up/down counter, and eight new rows are rapidly refreshed at 450 nanosecond intervals.