Abstract: A dynamically configurable arrangement for determining performance of a microprocessor. A plurality of functional units in a microprocessor are coupled to a performance counter, wherein the performance counter is incremented in response to occurrence of a predetermined event. A plurality of repeaters coupled between the plurality of functional units and the performance counter. Control circuitry coupled to the plurality of repeaters, wherein the control circuitry selectively enables the repeaters such that only one functional unit is coupled to the performance counter at a particular time.