Patents by Inventor Reese Reynolds

Reese Reynolds has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10580628
    Abstract: One process used to remove material from a surface is ion etching. In certain cases, ion etching involves delivery of both ions and a reactive gas to a substrate. The disclosed embodiments permit local high pressure delivery of reactive gas to a substrate while maintaining a much lower pressure on portions of the substrate that are outside of the local high pressure delivery area. In many cases, the low pressure is achieved by providing an injection head that confines the high pressure reactant delivery to a small area and vacuums away excess reactants and byproducts as they leave this small area and before they enter the larger substrate processing region. The disclosed injection head may be used to increase throughput while minimizing deleterious collisions between ions and other species present in the substrate processing region. The disclosed injection head may also be used in other types of semiconductor wafer processing.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 3, 2020
    Assignee: Lam Research Corporation
    Inventors: Ivan L. Berry, III, Thorsten Lill, Kenneth Reese Reynolds
  • Publication number: 20180047548
    Abstract: One process used to remove material from a surface is ion etching. In certain cases, ion etching involves delivery of both ions and a reactive gas to a substrate. The disclosed embodiments permit local high pressure delivery of reactive gas to a substrate while maintaining a much lower pressure on portions of the substrate that are outside of the local high pressure delivery area. In many cases, the low pressure is achieved by providing an injection head that confines the high pressure reactant delivery to a small area and vacuums away excess reactants and byproducts as they leave this small area and before they enter the larger substrate processing region. The disclosed injection head may be used to increase throughput while minimizing deleterious collisions between ions and other species present in the substrate processing region. The disclosed injection head may also be used in other types of semiconductor wafer processing.
    Type: Application
    Filed: October 25, 2017
    Publication date: February 15, 2018
    Inventors: Ivan L. Berry, III, Thorsten Lill, Kenneth Reese Reynolds
  • Patent number: 9837254
    Abstract: One process that may be used to remove material from a surface is ion etching. In certain cases, ion etching involves delivery of both ions and a reactive gas to a substrate. The disclosed embodiments permit local high pressure delivery of reactive gas to a substrate while maintaining a much lower pressure on portions of the substrate that are outside of the local high pressure delivery area. The low pressure is achieved by confining the high pressure reactant delivery to a small area and vacuuming away excess reactants and byproducts as they leave this small area and before they enter the larger substrate processing region. The disclosed techniques may be used to increase throughput while minimizing deleterious collisions between ions and other species present in the substrate processing region.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: December 5, 2017
    Assignee: Lam Research Corporation
    Inventors: Ivan L. Berry, III, Thorsten Lill, Kenneth Reese Reynolds
  • Patent number: 9460925
    Abstract: A substrate processing system that includes a substrate processing chamber having one or more sidewalls that at least partially define a substrate processing region and extend away from a bottom wall of the substrate processing chamber at an obtuse angle; a source material holder configured to hold a source material within the substrate processing region; a plasma gun operatively coupled to introduce a plasma beam into the substrate processing region; one or more magnets operatively arranged to generate a magnetic field that guides the plasma beam to the source material holder; and a substrate carrier configured to hold one or more substrates within the substrate processing region.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: October 4, 2016
    Assignee: SolarCity Corporation
    Inventors: Wei Wang, Jianming Fu, Zheng Xu, Kenneth Reese Reynolds, Ollivier Jacky Lefevre
  • Publication number: 20160126098
    Abstract: A substrate processing system that includes a substrate processing chamber having one or more sidewalls that at least partially define a substrate processing region and extend away from a bottom wall of the substrate processing chamber at an obtuse angle; a source material holder configured to hold a source material within the substrate processing region; a plasma gun operatively coupled to introduce a plasma beam into the substrate processing region; one or more magnets operatively arranged to generate a magnetic field that guides the plasma beam to the source material holder; and a substrate carrier configured to hold one or more substrates within the substrate processing region.
    Type: Application
    Filed: November 5, 2015
    Publication date: May 5, 2016
    Applicant: SOLARCITY CORPORATION
    Inventors: Wei Wang, Jianming Fu, Zheng Xu, Kenneth Reese Reynolds, Ollivier Jacky Lefevre
  • Publication number: 20160049281
    Abstract: One process that may be used to remove material from a surface is ion etching. In certain cases, ion etching involves delivery of both ions and a reactive gas to a substrate. The disclosed embodiments permit local high pressure delivery of reactive gas to a substrate while maintaining a much lower pressure on portions of the substrate that are outside of the local high pressure delivery area. The low pressure is achieved by confining the high pressure reactant delivery to a small area and vacuuming away excess reactants and byproducts as they leave this small area and before they enter the larger substrate processing region. The disclosed techniques may be used to increase throughput while minimizing deleterious collisions between ions and other species present in the substrate processing region.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 18, 2016
    Inventors: Ivan L. Berry, III, Thorsten Lill, Kenneth Reese Reynolds
  • Patent number: 9068263
    Abstract: The present invention relates to equipment used to manufacture PV cells or modules. In some embodiments, a gas delivery and gas exhaust system are provided for processing a plurality of substrates. The gas delivery and gas exhaust system are designed such that the substrates are exposed in a uniform manner to the gas.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: June 30, 2015
    Assignee: Sandvik Thermal Process, Inc.
    Inventors: Reese Reynolds, H. William Lucas, Jr., Tyke Johnson
  • Patent number: 8486835
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 16, 2013
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Tom L. Cadwell, Doris Mytton
  • Patent number: 8360411
    Abstract: The present invention relates to equipment used to manufacture PV cells or modules. In some embodiments, a support structure is provided that provides support for substrates used in the manufacture of PV cells or modules. The support structure provides support for the substrate at the edge, allows access to the rear of the substrate and is composed of materials that do not contaminate the substrate during processing.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: January 29, 2013
    Assignee: MRL Industries, Inc.
    Inventors: Reese Reynolds, Wail George Mansour, Mark Dipietro, Chetwyn Jones
  • Publication number: 20120085281
    Abstract: The present invention relates to in-line equipment used to process substrates. In some applications, the equipment is used in the in-line manufacture PV cells or modules. In some embodiments, a heating system is provided that comprises a plurality of heating technologies for the heat treatment of substrates wherein a first heating system is used to rapidly raise the substrate temperature to the desired set point and a second heating system is used to maintain the substrate at the temperature set point throughout the thermal treatment process.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 12, 2012
    Applicant: Sandvik Thermal Process, Inc.
    Inventors: Aubrey L. HELMS, JR., Kevin B. Peck, James T. Johnson, Pontus K.H. Nilsson, Reese Reynolds
  • Patent number: 7972703
    Abstract: Baffle wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. An all-silicon hot zone of a thermal furnace may include a silicon support tower placed within a silicon liner and supporting the polysilicon baffle wafers with silicon injector tube providing processing gas within the liner. The randomly oriented polysilicon may be used for other parts requiring a rugged member, for example, within a silicon processing chamber and for structural members.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: July 5, 2011
    Assignee: Ferrotec (USA) Corporation
    Inventors: James E. Boyle, Reese Reynolds, Ranaan Y. Zehavi, Robert W. Mytton, Tom L. Cadwell
  • Publication number: 20110018187
    Abstract: The present invention relates to equipment used to manufacture PV cells or modules. In some embodiments, a support structure is provided that provides support for substrates used in the manufacture of PV cells or modules. The support structure provides support for the substrate at the edge, allows access to the rear of the substrate and is composed of materials that do not contaminate the substrate during processing.
    Type: Application
    Filed: February 24, 2010
    Publication date: January 27, 2011
    Applicant: MRL INDUSTRIES, INC
    Inventors: Reese Reynolds, Wail George Mansour, Mark Dipietro, Chetwyn Jones
  • Publication number: 20100218725
    Abstract: The present invention relates to equipment used to manufacture PV cells or modules. In some embodiments, a gas delivery and gas exhaust system are provided for processing a plurality of substrates. The gas delivery and gas exhaust system are designed such that the substrates are exposed in a uniform manner to the gas.
    Type: Application
    Filed: February 24, 2010
    Publication date: September 2, 2010
    Applicant: MRL INDUSTRIES, INC.
    Inventors: Reese REYNOLDS, H. William Lucas, JR., Tyke Johnson
  • Patent number: 7713355
    Abstract: A silicon shelf tower for hatch thermal processing of silicon wafers in a vertical furnace. The tower includes at least three silicon legs joined to bases and having a vertical arrangement of slots. Silicon shelves are detachably loaded by sliding them through the slots in the side legs and into the slot of the back leg. A interlocking mechanism detachably locks the shelves to the back leg while the slots in the two side legs laterally constrains the shelves. The shelves include cutouts to allow a robot paddle to load and unload wafers to the shelves. Circular holes in the shelves relieve stress and prevent wafer sticking Preferably, the shelves are formed from randomly oriented polycrystalline silicon. The shelves and towers can alternatively be made of other materials such as quartz and silicon carbide.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: May 11, 2010
    Assignee: Integrated Materials, Incorporated
    Inventors: Ranaan Zehavi, Reese Reynolds
  • Publication number: 20100009123
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Application
    Filed: September 18, 2009
    Publication date: January 14, 2010
    Applicant: INTEGRATED MATERIALS, INC.
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Robert W. Mytton, Doris Mytton, Tom L. Cadwell
  • Patent number: 7625692
    Abstract: Systems and methods are described for improved yield and line width performance for liquid polymers and other materials. A method for minimizing precipitation of developing reactant by lowering a sudden change in pH includes: developing at least a portion of a polymer layer on a substrate with an initial charge of a developer fluid; then rinsing the polymer with an additional charge of the developer fluid so as to controllably minimize a subsequent sudden change in pH; and then rinsing the polymer with a charge of another fluid. An apparatus for minimizing fluid impingement force on a polymer layer to be developed on a substrate includes: a nozzle including: a developer manifold adapted to supply a developer fluid; a plurality of developer fluid conduits coupled to the developer manifold; a rinse manifold adapted to supply a rinse fluid; and a plurality of rinse fluid conduits coupled to the developer manifold.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: December 1, 2009
    Assignee: ASML Holding N.V.
    Inventors: Emir Gurer, Ed C. Lee, Murthy Krishna, Reese Reynolds, John Salois, Royal Cherry
  • Patent number: 7611989
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: November 3, 2009
    Assignee: Integrated Materials, Inc.
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Robert W. Mytton, Doris Mytton, legal representative, Tom L. Cadwell
  • Publication number: 20080152805
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 26, 2008
    Applicant: INTEGRATED MATERIALS, INC.
    Inventors: James E. BOYLE, Reese REYNOLDS, Raanan Y. ZEHAVI, Robert W. MYTTON, Tom L. CADWELL, Doris MYTTON
  • Patent number: 7255975
    Abstract: Systems and methods are described for improved yield and line width performance for liquid polymers and other materials. A method for minimizing precipitation of developing reactant by lowering a sudden change in pH includes: developing at least a portion of a polymer layer on a substrate with an initial charge of a developer fluid; then rinsing the polymer with an additional charge of the developer fluid so as to controllably minimize a subsequent sudden change in pH; and then rinsing the polymer with a charge of another fluid. An apparatus for minimizing fluid impingement force on a polymer layer to be developed on a substrate includes: a nozzle including: a developer manifold adapted to supply a developer fluid; a plurality of developer fluid conduits coupled to the developer manifold; a rinse manifold adapted to supply a rinse fluid; and a plurality of rinse fluid conduits coupled to the developer manifold.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: August 14, 2007
    Assignee: ASML Holding N.V.
    Inventors: Emir Gurer, Ed C. Lee, Murthy Krishna, Reese Reynolds, John Salois, Royal Cherry
  • Publication number: 20070169701
    Abstract: A tubular member formed of silicon staves and arranged in a circular pattern to form a central bore in which a wafer support tower can be inserted for batch thermal processing in an oven. The staves are formed along an axis with an interlocking keyway structure in which axially extending hooks engage axially extending catches formed in back of the hooks on neighboring staves. An adhesive, such as a silica-forming agent and silicon powder, coat the keyway structure before assembly and is cured after assembly, so as to bond the staves together. A similar structure may be used to form a plate structure from an array of smaller parts with interlocking structure formed between neighboring parts.
    Type: Application
    Filed: September 28, 2006
    Publication date: July 26, 2007
    Applicant: INTEGRATED MATERIALS, INC.
    Inventors: Reese REYNOLDS, Michael SKLYAR