Patents by Inventor Reetika K Agarwal

Reetika K Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Partial-fractional phase-locked loop with sigma delta modulator and finite impulse response filter
    Patent number: 11955979
    Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: April 9, 2024
    Inventors: Reetika K Agarwal, Abbas Komijani, Hongrui Wang
  • Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter
    Publication number: 20230403013
    Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Inventors: Reetika K Agarwal, Abbas Komijani, Hongrui Wang
  • Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and Finite Impulse Response Filter
    Publication number: 20230403014
    Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
    Type: Application
    Filed: August 9, 2023
    Publication date: December 14, 2023
    Inventors: Reetika K. Agarwal, Abbas Komijani, Hongrui Wang