Abstract: A dynamic random access memory (DRAM) for use in MPEG decoding includes d devices each having r rows and c columns with b bits per cell and p samples, where b*d is divisible by 8 and r*c is larger than a sum of upstream buffers in bytes and either 2 or 3 times 1.5*1*p divided by (b*d/8). First and second reference picture components are organized first along a depth axis (d) and then along rows (r) with complete lines of a component occupying the same row with the memory region occupied by each component being rectangular and third reference signal components are organized first along a depth axis and then along rows and occupying a largest possible part of each row in multiples of 8*(8/(b*d)).

Abstract: Data transfer and timing in an external DRAM memory of an MPEG decoder utilizes a repetitive pattern for synchronous writing and reading of data and data refresh including a sequence header at the beginning of a picture, a macroblock header for each of the macroblocks of a picture, and a plurality of repetitions of block decoding after each macroblock header decode.

Abstract: An MPEG decoder which distributes the processing load to a plurality of processors and units including an external memory and a bus interface unit, a de-multiplexing data processor, an image data processor, an inverse transform and reconstruction processor, and a prediction calculation unit. A video post-processing unit generates video data, and a serial port unit provides an output for audio data.

Abstract: Memory address generation circuitry includes two binary counters for generating addresses for application to an address bus. The least significant bits of one counter are connected to the address bus in bit positions corresponding to the most significant bits of the other counter whereby the two counters increment addresses in opposite directions. The mode of address generation permits addresses for data in normal order, data within data blocks in normal order and data blocks in reverse-bit order, and data within data blocks in bit-reverse order and data blocks in normal order. The circuitry has particular applicability in memory address generation when operating on data with algorithms for FFT operations in one or more dimensions.

Abstract: Circuitry for use in operating on block floating-point data where all data in a block has a scale factor associated therewith including a maximum scale register for storing the maximum scale factor of the data in a block, a subtractor for obtaining a difference value between the maximum scale factor and a data scale factor as the data is retrieved for operation, and a computer for adjusting the scale of retireved data by the difference prior to operation on the data. As the data in a block is operated on scale overflow is stored and used to adjust subsequent data as read from memory prior to operation thereon. A counter is provided for counting all scale overflow as a result of operations on all data in a block with the maximum scale register being updated based on the total count following operations on all data in the block.

Abstract: A digital filter processor employs four multiplier-accumulator cells and an output accumulator for receiving and accumulating all cell outputs. Data is provided to all cells in parallel, and finite impulse coefficients are applied serially to all cells. A plurality of registers and at least one multiplexer interconnect the cells for transmitting the coefficients between cells. The registers can be employed for sample rate reduction or decimation. A plurality of processors can be cascaded for processing an increased number of coefficients without a reduction in sample time. Alternatively, data can be recycled in a processor to accommodate a number of coefficients greater than the number of cells at a reduced sampled sample rate. A cell address is provided for selecting cell outputs during the reading of the filtered/processed data.