Patents by Inventor Regina Mara Amaral Fonseca

Regina Mara Amaral Fonseca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for automatic formal metastability fault analysis in an electronic design
    Patent number: 10769008
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. The method may include receiving, using at least one processor, an electronic design and analyzing the electronic design. The method may further include generating one or more preconditions representative of metastability effects at the output of at least one synchronizer associated with the electronic design. The method may also include generating, based upon, at least in part, the one or more preconditions, one or more properties configured to analyze a propagation of the metastability effects associated with the at least one synchronizer.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: September 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alberto Manuel Arias Drake, Andrea Iabrudi Tavares, Artur Melo Mota Costa, Fabiano Cruz Peixoto, Laiz Lipiainen Santos, Lucas Ferreira de Melo Diniz, Nathália Peixoto Reis, Patricia Sette Câmara Haizer, Regina Mara Amaral Fonseca, Tamires Vargas Capanema Franco Santos
  • System, method, and computer program product for property clustering associated with formal verification of an electronic circuit design
    Patent number: 10289798
    Abstract: The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ronalu Augusta Nunes Barcelos, Hudson Dyele Pinheiro de Oliveira, Mirlaine Aparecida Crepalde, Lucas Luz Reckziegel, Glauber Tadeu de Sousa Carmo, Augusto Amaral Mafra, Regina Mara Amaral Fonseca, Guilherme Henrique de Sousa Santos, Valdir Antoniazzi Júnior