Abstract: An artificial neural system employs digital elements that may be fabricated using state of the art technology. The system includes a plurality of digital neural processors, each of the processors containing at least one register for storing a number; a signal is applied to the register to selectively increment or decrement the number stored in the register; circuitry is provided for resetting the register and for processing the number stored in the register. The neural system is trained by incrementing and/or decrementing numbers stored in the registers.

Abstract: A charge coupled device (CCD) frequency divider circuit for dividing the frequency of an input signal comprises a CCD having main, drain, and feedback channels. Input signal charge is injected during each cycle of the input signal into a potential well under a storage electrode that retains a predetermined quantity of charge. Overflow from the storage electrode is detected by a sensing electrode that is normally maintained in a transfer state, causing the sensing electrode to switch to a barrier state. This allows the predetermined quantity of charge to advance to an output while the overflow is dumped out by the drain channel. However, when no overflow is present, the sensing electrode causes the input charge to be transferred into the feedback channel which circulates it to the storage electrode to combine with another input charge received by the storage electrode during a subsequent cycle of the input signal.

Abstract: A circuit for use in digital charge coupled systems provides successive indications of input binary value, until reset, without timing delays and without degeneration of the charge packets. A data input charge packet is provided to a storage electrode, and a series of standardized charge packets are also provided to the storage electrode at the data rate of the system. The latch circuit operates cyclically in internal cycles between the arrival of successive standardized charge packets. The concurrent presence of an input charge packet and a standardized charge packet results in charge overflow across a barrier in a first output data channel. This overflow causes a floating gate electrode that interconnects the first output channel with a second output channel to block transfer of the basic charge packet out the second output channel. It also causes the basic charge packet to be returned as a data input back to the storage electrode.

Abstract: A charge coupled device channel crossover circuit transfers charge packets in each of two different intersecting channels during each of a succession of transfer intervals defined by a pair of clocking signals of opposite phase and a pair of clock signal related pulse trains applied to various electrodes of the crossover circuit to provide changing potential biases. The crossover circuit includes a common transfer area at the intersection of the two channels, a pair of transfer gates within each channel on opposite sides of the transfer area and a pair of storage areas within each channel on opposite sides of the transfer gates from the transfer area.

Abstract: The problem of gradual dissipation of charge in charge packets in charge-coupled devices (CCDs) as the packets are successively shifted is overcome by a regenerator circuit which also provides a basic structure for effecting elemental logic and arithmetic functions. A standardized charge packet is injected along with a digitally valued but somewhat diminished charge packet into a potential well under a storage electrode arranged to retain a single charge packet. Overflow from the storage electrode region that represents only some part of a full charge packet is detected by a master sensing gate that controls a slave gate forming a shunt path for the full charge packet and that is normally maintained in a transfer state. The slave gate shifts to a barrier state when the overflow packet is present, however, permitting the full charge packet to advance along another electrode path.