Abstract: An imaging device and method of using is provided that requires no traditional optics but uses an addressable array of vertically oriented carbon nanotubes. The technique relies on the ability to reduce the nearest neighbor spacing between the carbon nanotubes to less than the wavelength of light used in traditional optical microscopes. The nanoscope can have a resolution of less than 100 nm. Electrophoresis deposition can be used to direct the assembly of the carbon nanotubes onto interconnects in an integrated circuit, which could be used to address the array. The device is portable, compact, and does not utilize complicated components. It also derives spatially resolved dielectric and chemical properties of a sample to be imaged.

Abstract: An imaging device and method of using is provided that requires no traditional optics but uses an addressable array of vertically oriented carbon nanotubes. The technique relies on the ability to reduce the nearest neighbor spacing between the carbon nanotubes to less than the wavelength of light used in traditional optical microscopes. The nanoscope can have a resolution of less than 100 nm. Electrophoresis deposition can be used to direct the assembly of the carbon nanotubes onto interconnects in an integrated circuit, which could be used to address the array. The device is portable, compact, and does not utilize complicated components. It also derives spatially resolved dielectric and chemical properties of a sample to be imaged.

Abstract: A device for determining the presence of a single cell and/or determining a state of a single cell includes a first nanotube disposed on a first electrode, and a second nanotube disposed on a second electrode, wherein the first and second nanotubes are spaced apart at a length that is smaller than a cell size to be detected. A method for determining the presence of a single biological cell includes sensing impedance between a first nanotube and a second nanotube. A method of manufacturing includes providing a nanotube, providing an electrode coated with an insulating material, wherein an aperture is defined in the insulating material through to the electrode, and using electrophoresis deposition to deposit a nanotube within the aperture and in electrical communication with the electrode.

Abstract: A device for determining the presence of a single cell and/or determining a state of a single cell includes a first nanotube disposed on a first electrode, and a second nanotube disposed on a second electrode, wherein the first and second nanotubes are spaced apart at a length that is smaller than a cell size to be detected. A method for determining the presence of a single biological cell includes sensing impedance between a first nanotube and a second nanotube. A method of manufacturing includes providing a nanotube, providing an electrode coated with an insulating material, wherein an aperture is defined in the insulating material through to the electrode, and using electrophoresis deposition to deposit a nanotube within the aperture and in electrical communication with the electrode.

Abstract: Improved nanotube devices and systems/methods for fabrication thereof are provided. The present disclosure provides systems/methods for depositing controlled numbers of nanotubes with specific properties at predefined locations for the fabrication of nanotube devices. The nanotube devices may be utilized in a range of applications. A bio-fuel cell system that does not require a proton exchange membrane separator and does not need a mediator to transfer charge is provided. This exemplary bio-fuel cell uses enzyme functionalized SWNTs for the anode/cathode. The absence of a membrane in the bio-fuel cell configuration opens up the possibility of other configurations that would otherwise be unfeasible. This includes a bio-fuel cell where the anode/cathode are on the same substrate. Since the electrodes can share the same substrate, the configuration may be integrated with a circuit device on the same substrate. An IC and its power source may be fabricated on the same silicon wafer.

Abstract: A nanotube device and a method of depositing nanotubes for device fabrication are disclosed. The method relates to electrophoretic deposition of nanotubes, and allows a control of the number of deposited nanotubes and positioning within a defined region.

Abstract: Improved nanotube devices and systems/methods for fabrication thereof are provided. The present disclosure provides systems/methods for depositing controlled numbers of nanotubes with specific properties at predefined locations for the fabrication of nanotube devices. The nanotube devices may be utilized in a range of applications. A bio-fuel cell system that does not require a proton exchange membrane separator and does not need a mediator to transfer charge is provided. This exemplary bio-fuel cell uses enzyme functionalized SWNTs for the anode/cathode. The absence of a membrane in the bio-fuel cell configuration opens up the possibility of other configurations that would otherwise be unfeasible. This includes a bio-fuel cell where the anode/cathode are on the same substrate. Since the electrodes can share the same substrate, the configuration may be integrated with a circuit device on the same substrate. An IC and its power source may be fabricated on the same silicon wafer.

Abstract: A method and apparatus are disclosed for fabricating a substrate having a plurality of circuit patterns. The substrate is exposed to a primary mask having a plurality of the desired circuit patterns, surrounded by one or more exclusion regions, and a secondary mask having a pattern corresponding to the exclusion regions that satisfies at least one design rule for a subsequent process. The primary and secondary masks are exposed on the substrate in any order before the resist patterns are developed. The pattern on the secondary mask may comprise, for example, an array of fill patterns. The pattern on the secondary mask may satisfy design rules for more than one process level so that a single secondary mask can be utilized for multiple process levels. In addition, the substrate only needs to be exposed to the secondary mask for process levels where the exclusion regions violate a design rule.

Abstract: A method of depositing nanotubes in a region defined by an aperture is disclosed. The method provides advantageous control over the number of nanotubes to be deposited, as well as the pattern and spacing of nanotubes. Electrophoretic deposition, along with proper configuration of the aperture, allows at least one nanotube to be deposited in a target region with nanometer scale precision. Pre-sorting of nanotubes, e.g., according to their geometries or other properties, may be used in conjunction with embodiments of the invention to facilitate fabrication of devices with specific performance requirements. The method is useful for many applications where it is desirable to deposit more than one nanotube in a defined region. For example, vertical field effect transistor (VFET) designs may benefit from having more than one nanotube forming a channel to allow more current to flow through the device.

Abstract: A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Abstract: A method and apparatus are disclosed for fabricating a substrate having a plurality of circuit patterns. The substrate is exposed to a primary mask having a plurality of the desired circuit patterns, surrounded by one or more exclusion regions, and a secondary mask having a pattern corresponding to the exclusion regions that satisfies at least one design rule for a subsequent process. The primary and secondary masks are exposed on the substrate in any order before the resist patterns are developed. The pattern on the secondary mask may comprise, for example, an array of fill patterns. The pattern on the secondary mask may satisfy design rules for more than one process level so that a single secondary mask can be utilized for multiple process levels. In addition, the substrate only needs to be exposed to the secondary mask for process levels where the exclusion regions violate a design rule.

Abstract: A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Abstract: A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Abstract: A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Abstract: A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.