Abstract: A multipurpose bus interface circuit for interfacing a first communications bus to a second communications bus where at least one of the buses is a command/response time division multiplexing data bus. The interface circuit includes a main controller for controlling the transfer of data between the first bus and a RAM. A microstore contains the software for the main controller, the software controlling the handling and interpretation of data to and from the first bus and processed by the main controller. A co-processor has direct access to the RAM and performs primarily the data processing function of the interface circuit. An interface module provides interface between the RAM and the second bus, the module formatting the data transmitted between the RAM and the second bus, whereby the main controller performs primarily to handle the input/output functions and the co-processor performs primarily to handle the data processing functions of the interface circuit.