Abstract: A device for controlling a clock signal phase to reduce the clock skew includes a clock signal generator, a pad circuit and a phase adjustment device. The clock signal generator is disposed in a chip for generating the clock signal. The pad circuit is disposed in the chip, and electrically connected between the clock signal generator and an external circuit, and includes an output buffer and an input buffer, wherein the output buffer transmits the clock signal to both the external circuit and the input buffer, and the input buffer further transmits the clock signal to a logic circuit module of the chip. The phase adjustment device is disposed in the chip and electrically connected between an output end of the input buffer and the logic circuit module of the chip for adjusting the clock signal required for the operation of the logic circuit module.

Abstract: A device for controlling a clock signal phase to reduce the clock skew is disclosed. The device includes a clock signal generator disposed in a chip for generating the clock signal, a pad circuit disposed in the chip, electrically connected between the clock signal generator and an external circuit, and including an output buffer and an input buffer, wherein the output buffer transmits the clock signal to both of the external circuit and the input buffer, and the input buffer further transmits the clock signal to a logic circuit module of the chip, and a phase adjustment device disposed in the chip and electrically connected between an output end of the input buffer and the logic circuit module of the chip for adjusting the clock signal required for the operation of the logic circuit module.