Patents by Inventor Rehan A. Zakai
Rehan A. Zakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10175122Abstract: Embodiments disclosed herein generally relate to a method for monitoring optical power in a HAMR device. In one embodiment, the method includes enhancing a thermal sensor bandwidth through advanced electrical detection techniques. The advanced electrical detection techniques include obtaining calibration waveform data for a thermal sensor by calibrating the thermal sensor, obtaining real-time waveform data for the thermal sensor that may deviate from the calibration waveform data, updating the calibration waveform data to include the real-time waveform data, repeating obtaining real-time waveform data and updating the calibration waveform data during writing operations. By updating the calibration waveform data, the bandwidth of the thermal sensor is determined by a fixed sampling time interval, and the thermal sensor rise time to steady state would not be a limitation to its response time.Type: GrantFiled: May 20, 2016Date of Patent: January 8, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: John T. Contreras, Lidu Huang, Shen Ren, Erhard Schreck, Rehan A. Zakai
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Patent number: 10056098Abstract: A data storage device is disclosed comprising a head actuated over a disk, wherein the head comprises a first sensor element and a second sensor element. When configured into a first single-ended mode, a bias signal is applied to the first sensor element to generate a first single-ended output signal based on a response of the first sensor element, and when configured into a second single-ended mode, the bias signal is applied to the second sensor element to generate a second single-ended output signal based on a response of the first sensor element. When configured into a differential mode, the bias signal is concurrently applied to the first sensor element and the second sensor element to generate a differential output signal based on a response of the first sensor element and the second sensor element.Type: GrantFiled: November 29, 2017Date of Patent: August 21, 2018Assignee: Western Digital Technologies, Inc.Inventors: Sukumar Rajauria, Erhard Schreck, John T. Contreras, Joey M. Poss, Rehan A. Zakai, Robert Smith, Barry C. Stipe
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Publication number: 20170336271Abstract: Embodiments disclosed herein generally relate to a method for monitoring optical power in a HAMR device. In one embodiment, the method includes enhancing a thermal sensor bandwidth through advanced electrical detection techniques. The advanced electrical detection techniques include obtaining calibration waveform data for a thermal sensor by calibrating the thermal sensor, obtaining real-time waveform data for the thermal sensor that may deviate from the calibration waveform data, updating the calibration waveform data to include the real-time waveform data, repeating obtaining real-time waveform data and updating the calibration waveform data during writing operations. By updating the calibration waveform data, the bandwidth of the thermal sensor is determined by a fixed sampling time interval, and the thermal sensor rise time to steady state would not be a limitation to its response time.Type: ApplicationFiled: May 20, 2016Publication date: November 23, 2017Inventors: John T. CONTRERAS, Lidu HUANG, Shen REN, Erhard SCHRECK, Rehan A. ZAKAI
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Patent number: 9030783Abstract: The embodiments disclosed generally relate to a read device in a magnetic recording head. The read device uses parametric excitation to injection lock the STO to an external AC signal with a frequency that is two times the resonance frequency, or more. The field from the media acting on the STO causes a change in the phase between the STO output and the external locking signal, which can be monitored using a phase detection circuit. The injection locking improves the STO signal to noise ratio and simplifies the detection circuit.Type: GrantFiled: February 6, 2014Date of Patent: May 12, 2015Assignee: HGST Netherlands B.V.Inventors: Patrick M. Braganca, Samir Y. Garzon, Bruce A. Gurney, Keyu Pi, Rehan A. Zakai, Jian Zhu
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Patent number: 8675311Abstract: An interleaved conductor structure for electrically connecting the read/write electronics to a read/write head in a hard disk drive is provided. The interleaved conductor structure may allow for an increased characteristic-impedance range, greater interference shielding and a reduction of signal loss that is contributed by a lossy conductive substrate. The electrical traces may have different widths, be offset, or even wrap around each other at the via connections.Type: GrantFiled: December 22, 2010Date of Patent: March 18, 2014Assignee: HGST Netherlands B.V.Inventors: John T. Contreras, Nobumasa Nishiyama, Edgar D. Rothenberg, Rehan A. Zakai, Yiduo Zhang
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Patent number: 8598460Abstract: An interleaved conductor structure for electrically connecting the read/write electronics to a read/write head in a hard disk drive is provided. The interleaved conductor structure may allow for an increased characteristic-impedance range, greater interference shielding and a reduction of signal loss that is contributed by a lossy conductive substrate. The electrical traces may have different widths, be offset, or even wrap around each other at the via connections.Type: GrantFiled: December 22, 2010Date of Patent: December 3, 2013Assignee: HGST Netherlands B.V.Inventors: John T. Contreras, Nobumasa Nishiyama, Edgar D. Rothenberg, Rehan A. Zakai, Yiduo Zhang
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Publication number: 20120162825Abstract: An interleaved conductor structure for electrically connecting the read/write electronics to a read/write head in a hard disk drive is provided. The interleaved conductor structure may allow for an increased characteristic-impedance range, greater interference shielding and a reduction of signal loss that is contributed by a lossy conductive substrate. The electrical traces may have different widths, be offset, or even wrap around each other at the via connections.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Inventors: JOHN T. CONTRERAS, Nobumasa Nishiyama, Edgar D. Rothenberg, Rehan A. Zakai, Yiduo Zhang
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Publication number: 20120160538Abstract: An interleaved conductor structure for electrically connecting the read/write electronics to a read/write head in a hard disk drive is provided. The interleaved conductor structure may allow for an increased characteristic-impedance range, greater interference shielding and a reduction of signal loss that is contributed by a lossy conductive substrate. The electrical traces may have different widths, be offset, or even wrap around each other at the via connections.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Inventors: John T. Contreras, Nobumasa Nishiyama, Edgar D. Rothenberg, Rehan A. Zakai, Yiduo Zhang
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Publication number: 20120160548Abstract: An interleaved conductor structure for electrically connecting the read/write electronics to a read/write head in a hard disk drive is provided. The interleaved conductor structure may allow for an increased characteristic-impedance range, greater interference shielding and a reduction of signal loss that is contributed by a lossy conductive substrate. The electrical traces may have different widths, be offset, or even wrap around each other at the via connections.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Inventors: JOHN T. CONTRERAS, Nobumasa Nishiyama, Edgar D. Rothenberg, Rehan A. Zakai, Yiduo Zhang
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System and method for effectively implementing an active termination circuit in an electronic device
Patent number: 6788099Abstract: A system and method for effectively transferring electronic information in an electronic device may include a transmission line that connects a source device and a destination device. The foregoing transmission line may be implemented to include a conductor A and a conductor B for transferring the electronic information. One or more active termination circuits may coupled to conductor A and conductor B for being dynamically switched between a differential mode termination configuration and a single-ended mode termination configuration with respect to the transmission line. Control logic may be configured to dynamically place the active termination circuit into the foregoing differential mode termination configuration during a differential transmission mode. Alternately, the control logic may place the active termination circuit into the foregoing single-ended mode termination configuration during a single-ended transmission mode.Type: GrantFiled: December 16, 2002Date of Patent: September 7, 2004Assignees: Sony Corporation, Sony Electronics Inc.Inventor: Rehan A. Zakai -
System and method for effectively implementing an active termination circuit in an electronic device
Publication number: 20040066210Abstract: A system and method for effectively transferring electronic information in an electronic device may include a transmission line that connects a source device and a destination device. The foregoing transmission line may be implemented to include a conductor A and a conductor B for transferring the electronic information. One or more active termination circuits may coupled to conductor A and conductor B for being dynamically switched between a differential mode termination configuration and a single-ended mode termination configuration with respect to the transmission line. Control logic may be configured to dynamically place the active termination circuit into the foregoing differential mode termination configuration during a differential transmission mode. Alternately, the control logic may place the active termination circuit into the foregoing single-ended mode termination configuration during a single-ended transmission mode.Type: ApplicationFiled: December 16, 2002Publication date: April 8, 2004Applicants: Sony Corporation, Sony Electronics, Inc.Inventor: Rehan A. Zakai -
Patent number: 6127891Abstract: A low voltage amplifier with gain boosting and a reduced power supply voltage requirement. A cascode amplifier circuit, biased with the power supply voltage, amplifies a pair of related, differential input signals based upon a pair of gain boost control signals and in accordance therewith provides a pair of gain boosted signals which correspond to the input signals. A gain boost control circuit, also biased with the power supply voltage, uses the differential input signals to generate the gain boost control signals. A class AB amplifier circuit, also biased with the power supply voltage, amplifies the gain boosted signals and in accordance therewith provides a class AB output signal which corresponds to the original input signals. The cascode amplifier circuit, gain boost control circuit and class AB amplifier circuit together operate with a minimum power supply voltage which equals a sum of one active transistor input bias potential and two active transistor output bias potentials(V.sub.DD(min) -V.sub.SS =V.Type: GrantFiled: April 5, 1999Date of Patent: October 3, 2000Assignee: National Semiconductor CorporationInventors: Rudy G. H. Eschauzier, Rehan A. Zakai