Patents by Inventor Rehan Kapadia
Rehan Kapadia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11890640Abstract: Methods of forming a monolayer of nanoparticles are described. The method may include forming an activated surface on a substrate. Methods may also include contacting the activated surface with a fluid including nanoparticles. Methods may further include forming a plurality of monolayers in the liquid on the activated surface. The plurality of nanoparticles may include a first monolayer of nanoparticles bonded to the activated surface. The plurality of nanoparticles may include a second monolayer of nanoparticles bonded to the first monolayer of nanoparticles. The bond strengths between a nanoparticle and the underlying substrate, between adjacent nanoparticles, and between nanoparticles of adjacent monolayers may be related by a specific relationship. The method may also include removing monolayers of the plurality of monolayers while retaining the first monolayer to form the substrate with the first monolayer. Systems for performing the methods and substrates resulting from the methods are also described.Type: GrantFiled: January 21, 2021Date of Patent: February 6, 2024Assignee: Nanoclear Technologies, Inc.Inventors: Harold Frank Greer, Rehan Kapadia, Angelica Saenz, David Webber
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Publication number: 20240021428Abstract: A method for processing a surface, comprising obtaining a substrate comprising an epitaxially grown semiconductor; reacting a surface of the semiconductor and/or a surface of a dielectric layer on the semiconductor, with a reactant comprising a gas or a plasma, to form a reactive layer on the dielectric layer and/or the semiconductor, wherein the reactive layer comprises a chemical compound including the reactant and elements of the dielectric layer or the semiconductor; and processing (e.g.Type: ApplicationFiled: July 13, 2023Publication date: January 18, 2024Applicants: California Institute of Technology, University of Southern CaliforniaInventors: Harold Frank Greer, Rehan Kapadia, Debargyha Sarkar
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Publication number: 20230215678Abstract: A HELAC device includes a semiconductor layer that absorbs incident photons, a graphene monolayer disposed over the semiconductor layer, and an insulator layer interposed between the semiconductor layer and graphene monolayer. The graphene monolayer is configured as a gate for the HELAC device while the insulator layer is configured to allow a voltage drop between the semiconductor layer and graphene. Advantageously, the HELAC device is configured to receive photons on an emitter surface and to emit hot electrons therefrom.Type: ApplicationFiled: September 8, 2022Publication date: July 6, 2023Inventors: Rehan KAPADIA, Hyun Uk CHAE, Ragib AHSAN, Subrata DAS
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Publication number: 20230151495Abstract: Methods described herein allow for a smoothing of a particular material on a substrate independently of smoothing a different material on the substrate. Both materials may be exposed to the same reactant but form different skins (e.g., reactive layers). One skin may allow for smoothing of one material, while the other skin may protect or preserve the underlying material. Removing one of the skins may result in a smoother underlying material. The skins may be formed by a dry process and removed by a wet process, or the skins may be formed by a wet process and removed by a dry process. The change of the reaction medium between wet and dry for reaction and removal may allow for highly selective chemistries to result in smoothing one material while not affecting the underlying substrate or other materials at the surface. Substrates produced by these methods are described herein.Type: ApplicationFiled: November 16, 2022Publication date: May 18, 2023Inventors: Harold Frank Greer, Rehan Kapadia
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Publication number: 20230095274Abstract: Methods of forming a monolayer of nanoparticles are described. The method may include forming an activated surface on a substrate. Methods may also include contacting the activated surface with a fluid including nanoparticles. Methods may further include forming a plurality of monolayers in the liquid on the activated surface. The plurality of nanoparticles may include a first monolayer of nanoparticles bonded to the activated surface. The plurality of nanoparticles may include a second monolayer of nanoparticles bonded to the first monolayer of nanoparticles. The bond strengths between a nanoparticle and the underlying substrate, between adjacent nanoparticles, and between nanoparticles of adjacent monolayers may be related by a specific relationship. The method may also include removing monolayers of the plurality of monolayers while retaining the first monolayer to form the substrate with the first monolayer. Systems for performing the methods and substrates resulting from the methods are also described.Type: ApplicationFiled: January 21, 2021Publication date: March 30, 2023Inventors: Harold Frank GREER, Rehan KAPADIA, Angelica SAENZ, David WEBBER
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Patent number: 10087547Abstract: This disclosure provides systems, methods, and apparatus related to the growth of single crystal III-V semiconductors on amorphous substrates. In one aspect, a shape of a semiconductor structure to be formed on an amorphous substrate is defined in a resist disposed on the amorphous substrate. A boron group element is deposited over the amorphous substrate. A ceramic material is deposited on the boron group element. The resist is removed from the amorphous substrate. The ceramic material is deposited to cover the boron group element. The amorphous substrate and materials deposited thereon are heated in the presence of a gas including a nitrogen group element to grow a single crystal semiconductor structure comprising the boron group element and the nitrogen group element.Type: GrantFiled: November 17, 2016Date of Patent: October 2, 2018Assignee: The Regents of the University of CaliforniaInventors: Kevin Chen, Rehan Kapadia, Ali Javey
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Publication number: 20170175290Abstract: This disclosure provides systems, methods, and apparatus related to the growth of single crystal III-V semiconductors on amorphous substrates. In one aspect, a shape of a semiconductor structure to be formed on an amorphous substrate is defined in a resist disposed on the amorphous substrate. A boron group element is deposited over the amorphous substrate. A ceramic material is deposited on the boron group element. The resist is removed from the amorphous substrate. The ceramic material is deposited to cover the boron group element. The amorphous substrate and materials deposited thereon are heated in the presence of a gas including a nitrogen group element to grow a single crystal semiconductor structure comprising the boron group element and the nitrogen group element.Type: ApplicationFiled: November 17, 2016Publication date: June 22, 2017Applicant: The Regents of the University of CaliforniaInventors: Kevin Chen, Rehan Kapadia, Ali Javey
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Patent number: 9161429Abstract: A neutron generator includes a conductive substrate comprising a plurality of conductive nanostructures with free-standing tips and a source of an atomic species to introduce the atomic species in proximity to the free-standing tips. A target placed apart from the substrate is voltage biased relative to the substrate to ionize and accelerate the ionized atomic species toward the target. The target includes an element capable of a nuclear fusion reaction with the ionized atomic species to produce a one or more neutrons as a reaction by-product.Type: GrantFiled: April 19, 2012Date of Patent: October 13, 2015Assignee: The Regents of the University of CaliforniaInventors: Thomas Schenkel, Arun Persaud, Rehan Kapadia, Ali Javey, Constance Chang-Hasnain, Ivo Rangelow, Joe Kwan
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Publication number: 20140290737Abstract: A composition comprising a substrate, a polycrystalline III-V semiconductor layer, and an oxide layer disposed above the polycrystalline III-V semiconductor layer is described. A growth method that enables fabrication of continuous thin films of polycrystalline indium phosphide (InP) directly on metal foils is described. The method describes the deposition of an indium (In) thin film (up to 20 microns thick) directly on molybedenum (Mo) foil, followed by the deposition of a thin oxide capping layer (up to 1 micron thick). This capping layer prevents dewetting of the In from the substrate during subsequent high temperature processing steps. The Mo/In/Capping Layer stack is then heated in the presence of phosphorous precursors, causing supersaturation of the liquid indium with phosphorous, followed by precipitation of InP. These polycrystalline III-V films have grain sizes 100-200 microns, minority carrier lifetimes >2 ns and hall mobilities of 500 cm?2/V-s.Type: ApplicationFiled: April 2, 2014Publication date: October 2, 2014Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Ali Javey, Zhibin Yu, Rehan Kapadia
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Patent number: 8709350Abstract: An ion source includes a conductive substrate, the substrate including a plurality of conductive nanostructures with free-standing tips formed on the substrate. A conductive catalytic coating is formed on the nanostructures and substrate for dissociation of a molecular species into an atomic species, the molecular species being brought in contact with the catalytic coating. A target electrode placed apart from the substrate, the target electrode being biased relative to the substrate with a first bias voltage to ionize the atomic species in proximity to the free-standing tips and attract the ionized atomic species from the substrate in the direction of the target electrode.Type: GrantFiled: April 19, 2012Date of Patent: April 29, 2014Assignee: The Regents of the University of CaliforniaInventors: Thomas Schenkel, Arun Persaud, Rehan Kapadia, Ali Javey
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Publication number: 20130044846Abstract: A neutron generator includes a conductive substrate comprising a plurality of conductive nanostructures with free-standing tips and a source of an atomic species to introduce the atomic species in proximity to the free-standing tips. A target placed apart from the substrate is voltage biased relative to the substrate to ionize and accelerate the ionized atomic species toward the target. The target includes an element capable of a nuclear fusion reaction with the ionized atomic species to produce a one or more neutrons as a reaction by-product.Type: ApplicationFiled: April 19, 2012Publication date: February 21, 2013Applicant: Regents of the University of CaliforniaInventors: Thomas Schenkel, Arun Persaud, Rehan Kapadia, Ali Javey, Constance Chang-Hasnain, Ivo Rangelow, Joe Kwan
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Publication number: 20120273342Abstract: An ion source includes a conductive substrate, the substrate including a plurality of conductive nanostructures with free-standing tips formed on the substrate. A conductive catalytic coating is formed on the nanostructures and substrate for dissociation of a molecular species into an atomic species, the molecular species being brought in contact with the catalytic coating. A target electrode placed apart from the substrate, the target electrode being biased relative to the substrate with a first bias voltage to ionize the atomic species in proximity to the free-standing tips and attract the ionized atomic species from the substrate in the direction of the target electrode.Type: ApplicationFiled: April 19, 2012Publication date: November 1, 2012Applicant: Regents of the University of CaliforniaInventors: Thomas Schenkel, Arun Persaud, Rehan Kapadia, Ali Javey