Abstract: Brightness values of image frames are collected and counted to form a brightness distribution. The brightness distribution of the image frames is compared with predetermined brightness distributions. Brightness values of all pixels of successive image frames are adjusted according to a result of the comparison, so as to improve image contrast.

Abstract: Selecting a corresponding procedure of dithering according to a general pattern of gray levels of sub-pixels of each color of an input image. This will enable the input image to be displayed on a display with a lower bit depth.

Abstract: A video controller including a switching device, an analog-to-digital converter and a digital video processor is provided. The switching device is for receiving an analog video sync signal and a first analog video signal, and combining the analog video sync signal with the first analog video signal to form a mixing signal according to a switching control signal. The analog video sync signal includes a specific video signal and a sync signal. A frequency of the switching control signal relates to a frequency of the sync signal. The analog-to-digital converter converts the mixing signal into a digital signal according to a sampling control signal. The digital video processor receives the digital signal and decodes the digital signal to generate a digital video sync signal and a first digital video signal.

Abstract: A system for parallel data transmission including a master device and a slave device is provided. The master device includes a first and a second I/O ports for outputting a read signal and a write signal, respectively. The slave device includes a third and a fourth I/O ports electrically coupled to the first and the second I/O ports, respectively. When the master device outputs the read or the write signal, the slave device transmits status information of the slave device to the master device after the master device has transmitted an address latch enable signal and before the slave device receives the address latch enable signal which is active. The master device outputs an address signal after transmitting the address latch enable signal and latches the address signal for the addressing for reading or writing data after the slave device has received the address latch enable signal.

Abstract: A display with charge function and a display controller thereof are provided. The display provided by the present invention includes a display controller and a charge base, wherein the display controller is built-in in the display, and includes a voltage output unit and a voltage detecting/regulating unit. The voltage output unit is used to provide an output voltage according to a pulse width modulation (PWM) signal. The voltage detecting/regulating unit is used to detect the output voltage output by the voltage output unit, and generate a regulating signal accordingly to regulate the pulse width of the PWM signal. The charge base is disposed on the display for charging a storage device on the charge base according to the output voltage output by the voltage output unit, wherein the voltage value of the output voltage output by the voltage output unit is followed by the pulse width of the PWM signal.

Abstract: Brightness values of image frames are collected and counted to form a brightness distribution. The brightness distribution of the image frames is compared with predetermined brightness distributions. Brightness values of all pixels of successive image frames are adjusted according to a result of the comparison, so as to improve image contrast.

Abstract: Selecting a corresponding procedure of dithering according to a general pattern of gray levels of sub-pixels of each color of an input image. This will enable the input image to be displayed on a display with a lower bit depth.

Abstract: A system for parallel data transmission including a master device and a slave device is provided. The master device includes a first and a second I/O ports for outputting a read signal and a write signal, respectively. The slave device includes a third and a fourth I/O ports electrically coupled to the first and the second I/O ports, respectively. When the master device outputs the read or the write signal, the slave device transmits status information of the slave device to the master device after the master device has transmitted an address latch enable signal and before the slave device receives the address latch enable signal which is active. The master device outputs an address signal after transmitting the address latch enable signal and latches the address signal for the addressing for reading or writing data after the slave device has received the address latch enable signal.