Patents by Inventor Reid Copeland
Reid Copeland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11886848Abstract: A method, system, and computer-readable medium for binary translation cause a binary translator to combine raw binary code and compiler-produced metadata associated with a compiled program module. The binary translator is caused to further reconcile, using the compiler-produced metadata, original compiler-produced control flow information with how lower-level machine instructions comprise a control flow in the raw binary code, and original compiler-produced aliasing information with how lower-level machine instructions access the memory locations described by the aliasing information according to predetermined criteria. The binary translator further caused to prevent, copy propagation of values in temporary variables for decimal computations beyond offsets in the machine instructions where the temporary variables are killed.Type: GrantFiled: May 25, 2022Date of Patent: January 30, 2024Assignee: International Business Machines CorporationInventors: Toshihiko Koju, Reid Copeland, David Kevin Siegwart, Jordan Ryan Zannier, Allan H. Kielstra
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Publication number: 20230385041Abstract: A method, system, and computer-readable medium for binary translation cause a binary translator to combine raw binary code and compiler-produced metadata associated with a compiled program module. The binary translator is caused to further reconcile, using the compiler-produced metadata, original compiler-produced control flow information with how lower-level machine instructions comprise a control flow in the raw binary code, and original compiler-produced aliasing information with how lower-level machine instructions access the memory locations described by the aliasing information according to predetermined criteria. The binary translator further caused to prevent, copy propagation of values in temporary variables for decimal computations beyond offsets in the machine instructions where the temporary variables are killed.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Inventors: Toshihiko Koju, REID COPELAND, David Kevin Siegwart, Jordan Ryan Zannier, ALLAN H. KIELSTRA
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Patent number: 11663004Abstract: An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.Type: GrantFiled: February 26, 2021Date of Patent: May 30, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Mark Schwarz, Kerstin Claudia Schelm, Petra Leber, Silvia Melitta Mueller, Reid Copeland, Xin Guo, Cedric Lichtenau
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Patent number: 11620153Abstract: Instruction interrupt suppression for an overflow condition. An instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per-instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.Type: GrantFiled: February 4, 2019Date of Patent: April 4, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cedric Lichtenau, Jonathan D. Bradbury, Reid Copeland, Petra Leber
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Patent number: 11593080Abstract: Dataflow optimization by dead store elimination focusing on logically dividing a contiguous storage area into different portions by use to allow a different number and type of dataflow and dead store techniques on each portion. A first storage portion, containing the storage for control flow related metadata, is split from a remaining storage portion. Liveness analysis is executed on the first storage portion using bitvectors with each bit representing four bytes. The remaining storage portion, containing the temporary storage for computational values, is processed using a deadness-range-based dataflow analysis. IN and OUT sets for each basic block are generated by processing blocks GEN and KILL sets by performing a backwards intersection dataflow analysis. Stores that write to the set of dead ranges in the IN sets of blocks are eliminated as dead stores.Type: GrantFiled: December 17, 2021Date of Patent: February 28, 2023Assignee: International Business Machines CorporationInventors: Jordan Ryan Zannier, Reid Copeland
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Patent number: 11531546Abstract: An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.Type: GrantFiled: March 8, 2021Date of Patent: December 20, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Mark Schwarz, Stefan Payer, Petra Leber, Kerstin Claudia Schelm, Michael Klein, Timothy Slegel, Reid Copeland, Xin Guo
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Patent number: 11442726Abstract: Vector pack and unpack instructions are described. An instruction to perform a conversion between one decimal format and another decimal format is executed, in which the one decimal format or the other decimal format is a zoned decimal format. The executing includes obtaining a value from at least one register specified using the instruction. At least a portion of the value is converted from the one decimal format to the other decimal format different from the one decimal format to provide a converted result. A result obtained from the converted result is written into a single register specified using the instruction.Type: GrantFiled: February 26, 2021Date of Patent: September 13, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Mark Schwarz, Timothy Slegel, Jonathan D. Bradbury, Michael Klein, Reid Copeland, Xin Guo
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Publication number: 20220283818Abstract: An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.Type: ApplicationFiled: March 8, 2021Publication date: September 8, 2022Inventors: Eric Mark Schwarz, Stefan Payer, Petra Leber, Kerstin Claudia Schelm, Michael Klein, Timothy Slegel, Reid Copeland, Xin Guo
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Publication number: 20220276867Abstract: An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.Type: ApplicationFiled: February 26, 2021Publication date: September 1, 2022Inventors: Eric Mark Schwarz, Kerstin Claudia Schelm, Petra Leber, Silvia Melitta Mueller, Reid Copeland, Xin Guo, Cedric Lichtenau
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Publication number: 20220276866Abstract: Vector pack and unpack instructions are described. An instruction to perform a conversion between one decimal format and another decimal format is executed, in which the one decimal format or the other decimal format is a zoned decimal format. The executing includes obtaining a value from at least one register specified using the instruction. At least a portion of the value is converted from the one decimal format to the other decimal format different from the one decimal format to provide a converted result. A result obtained from the converted result is written into a single register specified using the instruction.Type: ApplicationFiled: February 26, 2021Publication date: September 1, 2022Inventors: Eric Mark Schwarz, Timothy Slegel, Jonathan D. Bradbury, Michael Klein, Reid Copeland, Xin Guo
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Patent number: 11360769Abstract: An instruction to perform scaling, converting and splitting operations is executed. The executing the instruction includes scaling an input value in one format to provide a scaled result. The scaled result is converted from the one format to provide a converted result in another format. The converted result is split into multiple parts, and one or more parts of the multiple parts are placed in a selected location.Type: GrantFiled: February 26, 2021Date of Patent: June 14, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Mark Schwarz, Petra Leber, Kerstin Claudia Schelm, Silvia Melitta Mueller, Reid Copeland, Xin Guo, Cedric Lichtenau
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Patent number: 11099853Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.Type: GrantFiled: February 15, 2019Date of Patent: August 24, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cedric Lichtenau, Reid Copeland, Petra Leber, Silvia M. Mueller, Jonathan D. Bradbury, Xin Guo
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Patent number: 11023205Abstract: Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.Type: GrantFiled: February 15, 2019Date of Patent: June 1, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cedric Lichtenau, Reid Copeland, Petra Leber, Silvia M. Mueller, Jonathan D. Bradbury, Xin Guo
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Patent number: 11003453Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: GrantFiled: December 17, 2019Date of Patent: May 11, 2021Assignee: International Business Machines CorporationInventors: Carlos Cavanna, Reid Copeland, Chad McIntyre, Ali Sheikh
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Patent number: 10776255Abstract: A method for automatic verification of optimization of high level constructs includes generating a first executable code by compiling a computer program that includes a high level construct. The compiling includes generating a first set of machine instructions for the high level construct and storing compile-time information for the high level construct. The method further includes optimizing the first executable code which includes converting the first executable code into an intermediate language representation. The optimization further includes generating a second executable code. For this, the method includes generating a second set of machine instructions for the high level construct from the intermediate language representation. If the behavior of the first set of machine instructions and the second set of machine instructions matches, the second set of machine instructions is included in the second executable code, otherwise the first set of machine instructions is included.Type: GrantFiled: July 31, 2019Date of Patent: September 15, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Iain Alexander Ireland, Reid Copeland, Allan H. Kielstra, David Siegwart, Toshihiko Koju
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Publication number: 20200264890Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Cedric LICHTENAU, Reid COPELAND, Petra LEBER, Silvia M. MUELLER, Jonathan D. BRADBURY, Xin GUO
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Publication number: 20200264840Abstract: Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Cedric LICHTENAU, Reid COPELAND, Petra LEBER, Silvia M. MUELLER, Jonathan D. BRADBURY, Xin GUO
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Publication number: 20200249982Abstract: Instruction interrupt suppression for an overflow condition. An instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per-instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.Type: ApplicationFiled: February 4, 2019Publication date: August 6, 2020Inventors: Cedric Lichtenau, Jonathan D. Bradbury, Reid Copeland, Petra Leber
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Publication number: 20200125366Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: ApplicationFiled: December 17, 2019Publication date: April 23, 2020Applicant: International Business Machines CorporationInventors: Carlos CAVANNA, Reid COPELAND, Chad MC INTYRE, Ali SHEIKH
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Patent number: 10534612Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.Type: GrantFiled: March 28, 2017Date of Patent: January 14, 2020Assignee: International Business Machines CorporationInventors: Carlos Cavanna, Reid Copeland, Chad McIntyre, Ali Sheikh