Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor, the method comprising detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

Abstract: A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters, reconfiguring a compiler for the selected architecture parameters, compiling the benchmark, reconfiguring a data processor simulator to the selected architecture parameters, running the complied benchmark on the reconfigured simulator, automatically synthesizing an integrated circuit physical layout and evaluating performance of the selected architecture parameters against predetermined criteria. The method varies the selected architecture parameters upon failure to meet criteria until evaluation of the selected architecture parameters meets the criteria. The method selects a number of datapath clusters to avoid too many input/output ports in data registers.

Abstract: A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters, reconfiguring a compiler for the selected architecture parameters, compiling the benchmark, reconfiguring a data processor simulator to the selected architecture parameters, running the complied benchmark on the reconfigured simulator, automatically synthesizing an integrated circuit physical layout and evaluating performance of the selected architecture parameters against predetermined criteria. The method varies the selected architecture parameters upon failure to meet criteria until evaluation of the selected architecture parameters meets the criteria.

Abstract: An improved method is provided for performing register allocation in a compiler. This method determines the allocation of a plurality R of registers of a processor for use during the execution of a software program. The register allocation process is treated as a graph-coloring problem, such that an interference graph is constructed for the software program, the graph is simplified, and an R-coloring the interference graph to the extent possible is attempted. Then, spill code is inserted in the software program each for each uncolored node of the graph, a new interference graph is constructed, and the process is repeated. During the simplification process, nodes with degree greater than or equal to R are removed from the graph in an order dictated by a spill cost metric. During the coloring process, these same nodes are reinserted in the graph in an order dictated by reapplying the spill cost metric.

Abstract: A method of generating profiled optimized code using user interface (17) that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided. A program (11) is compiled in a compiler (13) with two or more compiler options such as size and speed and the resulting executables (14) are profiled (15). The results of the profiles (19) are analyed in a solver (21) for generating sets of useful solutions (23) wherein the sets have methods of compiling at the function level. The useful solutions (23) are displayed (18) at the user interface (17) to allow the user to visually understand, inspect and manipulate compiler options to select compiler options (13a) for the program.

Abstract: A data processing system with a microprocessor that has an instruction execution pipeline that includes fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execution packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. An add (k) constant to program counter (ADDKPC) instruction is provided, such that a parameter specified by the ADDKPC instruction is combined with a value provided by a program counter of microprocessor. The ADDKPC instruction can also specify a number of delay slots after a branch instruction to be filled with virtual NOP instructions such that memory is not wasted with useless NOP instructions. An ADDKPC instruction can provide a relative address for use as a return address. A plurality of predicated ADDKPC instructions can provide a return address selected from a plurality of return addresses.

Abstract: A user interface that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided.

Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.

Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.

Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.

Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.

Abstract: A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers (“GPRs” 102)and an arithmetic logic unit (“ALU” 104), capable of performing arithmetic operations and Boolean operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN)capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.

Abstract: A method of generating profiled optimized code using user interface (17) that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided. A program (11) is compiled in a compiler (13) with two or more compiler options such as size and speed and the resulting executables (14) are profiled (15). The results of the profiles (19) are analyed in a solver (21) for generating sets of useful solutions (23) wherein the sets have methods of compiling at the function level. The useful solutions (23) are displayed (18) at the user interface (17) to allow the user to visually understand, inspect and manipulate compiler options to select compiler options (13a) for the program.

Abstract: A method of producing a computer program for a computer capable of operating in a plurality of disjoint instruction sets. The method produces a plurality of independently callable functions. For each function the method determines a target instruction set employed by the function. The method provides the function with a name corresponding to the target instruction set. The function name is preferably a modification of a user provided function name corresponding to the target instruction set. The method identifies each call of another independent function and provides each with a name corresponding to the target instruction set. The method produces a veneer function for each function and for each other instruction set. The veneer functions include changing the computer from operating in the other instruction set to operating in the target instruction set, calling the corresponding function, changing the computer to operate in the other instruction set, and a return command.

Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.

Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.