Patents by Inventor Reid Harrison

Reid Harrison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reflectometry test system using a sliding pseudo-noise reference
    Patent number: 7548071
    Abstract: A technique for reflectometry testing of a signal path is disclosed. The technique includes injecting a test signal based on a probe pseudo-noise sequence into the signal path and obtaining a response signal. A sliding reference pseudo-noise sequence is correlated against the response signal. Both the probe sequence and the reference sequence are generated at a chip rate. The correlation is obtained for integer chip time delays, and sub-chip resolution of a peak correlation delay is estimated from at least two samples of the correlation.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: June 16, 2009
    Assignee: University of Utah Research Foundation
    Inventors: Reid Harrison, Cynthia Furse, Chirag Sharma
  • Flip chip metallization method and devices
    Patent number: 7388288
    Abstract: Interconnect metallization schemes and devices for flip chip bonding are disclosed and described. Metallization schemes include an adhesion layer, a diffusion barrier layer, a wetable layer, and a wetting stop layer. Various thicknesses and materials for use in the different layers are disclosed and are particularly useful for metallization in implantable electronic devices such as neural electrode arrays.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: June 17, 2008
    Assignees: University of Utah Research Foundation, Fraunhofer-Gesellschaft zur Foerderung der angewan
    Inventors: Florian Solzbacher, Reid Harrison, Richard A. Normann, Hans-Hermann Oppermann, Lothar Dietrich, Matthias Klein, Michael Töpper
  • FLIP CHIP METALLIZATION METHOD AND DEVICES
    Publication number: 20080096379
    Abstract: Interconnect metallization schemes and devices for flip chip bonding are disclosed and described. Metallization schemes include an adhesion layer, a diffusion barrier layer, a wettable layer, and a wetting stop layer. Various thicknesses and materials for use in the different layers are disclosed and are particularly useful for metallization in implantable electronic devices such as neural electrode arrays.
    Type: Application
    Filed: December 1, 2006
    Publication date: April 24, 2008
    Inventors: Florian Solzbacher, Reid Harrison, Richard Normann
  • In vivo implantable coil assembly
    Publication number: 20080021525
    Abstract: An in-vivo implantable coil assembly includes a planar coil having at least one coil layer formed from conductive traces disposed in or on a polymer matrix. A ferrite platelet is bonded to a surface of the polymer matrix. Methods of making and using the in-vivo implantable coil assembly are also disclosed.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 24, 2008
    Inventors: Florian Solzbacher, Reid Harrison, Richard Normann, Sohee Kim
  • Reflectometry test system using a sliding pseudo-noise reference
    Publication number: 20070194796
    Abstract: A technique for reflectometry testing of a signal path is disclosed. The technique includes injecting a test signal based on a probe pseudo-noise sequence into the signal path and obtaining a response signal. A sliding reference pseudo-noise sequence is correlated against the response signal. Both the probe sequence and the reference sequence are generated at a chip rate. The correlation is obtained for integer chip time delays, and sub-chip resolution of a peak correlation delay is estimated from at least two samples of the correlation.
    Type: Application
    Filed: January 30, 2007
    Publication date: August 23, 2007
    Inventors: Reid Harrison, Cynthia Furse, Chirag Sharma