Patents by Inventor Reid J. Riedlinger

Reid J. Riedlinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10552270
    Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Eric J. DeHaemer, Arijit Biswas, Reid J. Riedlinger, Ian M. Steiner
  • Publication number: 20180181474
    Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Eric J. DeHaemer, Arijit Biswas, Reid J. Riedlinger, Ian M. Steiner
  • Patent number: 8423832
    Abstract: A system for preventing processor errors in accordance with one exemplary embodiment of the present disclosure has a processor core, a patch, and a controller. The patch configures the processor core to detect occurrences of an event indicative of an imminent error in the processor core. The controller is configured to adjust, in response to a detection of an occurrence of the event by the processor core, a clock signal or a power signal provided to the processor core such that the imminent error is prevented.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: April 16, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Reid J. Riedlinger, Douglas John Cutter, Rich McGowen, II
  • Patent number: 8020038
    Abstract: A processor comprises a processor core and a controller. The processor core has an execution unit configured to execute instructions and to attempt to perform at least one operation in executing one of the instructions. The processor core is configured to detect a processor error associated with the at least one operation. The controller is configured to change an operating point of the processor core in response to a detection of the processor error such that the processor core operates at a new operating point, and the processor core is configured to retry the at least one operation while the processor core is operating at the new operating point.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: September 13, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Reid J. Riedlinger, Steven F. Liepe, Douglas John Cutter
  • Patent number: 7590509
    Abstract: A processor comprises a chip, a temperature sensing device, a processor core, and a controller. The temperature sensing device, the processor core, and the controller are integrated on the chip. The controller is configured to set, based on the temperature sensing device, the processor core to a plurality of specified operating points to enable testing of the specified operating points. Each of the operating points is defined by a different temperature and frequency combination, and the processor core is configured to run a set of test codes at each of the operating points.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: September 15, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Reid J. Riedlinger, Douglas John Cutter
  • Publication number: 20080155321
    Abstract: A processor comprises a processor core and a controller. The processor core has an execution unit configured to execute instructions and to attempt to perform at least one operation in executing one of the instructions. The processor core is configured to detect a processor error associated with the at least one operation. The controller is configured to change an operating point of the processor core in response to a detection of the processor error such that the processor core operates at a new operating point, and the processor core is configured to retry the at least one operation while the processor core is operating at the new operating point.
    Type: Application
    Filed: September 28, 2006
    Publication date: June 26, 2008
    Inventors: Reid J. Riedlinger, Steven F. Liepe, Douglas John Cutter
  • Publication number: 20080126826
    Abstract: A system for preventing processor errors in accordance with one exemplary embodiment of the present disclosure has a processor core, a patch, and a controller. The patch configures the processor core to detect occurrences of an event indicative of an imminent error in the processor core. The controller is configured to adjust, in response to a detection of an occurrence of the event by the processor core, a clock signal or a power signal provided to the processor core such that the imminent error is prevented.
    Type: Application
    Filed: November 7, 2006
    Publication date: May 29, 2008
    Inventors: Reid J. Riedlinger, Douglas John Cutter, Rich McGowen
  • Patent number: 7146457
    Abstract: Systems and methods are provided for searching at least one content addressable memory entry associated with a content addressable memory (CAM). A given content addressable memory entry comprises a plurality of CAM fields. At least one input selector controls access to the plurality of CAM fields, such that retrieval of a subset of the plurality of CAM fields is selectively enabled. A match evaluator compares an enabled subset of CAM fields to a search value.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: December 5, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kuldeep Simha, Reid J. Riedlinger
  • Publication number: 20040053510
    Abstract: A system and method of a RAM cell write circuit of a multi-ported RAM cell, including a first Field Effect Transistor (FET) having a gate connected to a first port not write bitline, and a second FET having a gate connected to a first port write wordline and, clear logic controlled by the first bitline and first wordline, the clear logic setting the memory element to a first value when said first bitline and said first wordline are active.
    Type: Application
    Filed: September 16, 2002
    Publication date: March 18, 2004
    Inventors: Casey J. Little, Reid J. Riedlinger