Patents by Inventor Reid Wistort

Reid Wistort has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080046789
    Abstract: This patent describes a method for varying the amplitude and frequency of power supply oscillations produced by content addressable memories or other critical circuits using BIST. Supply oscillations are produced by performing noisy (high switching activity—high current demand) searches followed by quiet (low switching activity—low current demand) searches. The amplitude and frequency of oscillations can be varied by changing the number of noisy and quiet searches e.g. pattern 1-noisy quiet, noisy, quiet; pattern 2-noisy, noisy, quiet, noisy, noisy, quiet, etc. By going through different patterns the current demand from the CAM macro increases the likelihood of producing worst—case noise and enables testing of CAM operation as well as surrounding circuitry in these noisy conditions.
    Type: Application
    Filed: August 21, 2006
    Publication date: February 21, 2008
    Inventors: Igor Arsovski, Valerie Chickanosky, Rahul Nadkarni, Michael Oucllette, Reid Wistort
  • Publication number: 20050184775
    Abstract: A delay locked loop for use in an integrated circuit device includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.
    Type: Application
    Filed: February 23, 2004
    Publication date: August 25, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold Pilo, Reid Wistort
  • Publication number: 20050184776
    Abstract: A delay locked loop for use in an integrated circuit device includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.
    Type: Application
    Filed: February 24, 2004
    Publication date: August 25, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold Pilo, Reid Wistort