Abstract: Method for wireless data interchange between circuit units within a package, and circuit arrangement for performing the method. The invention provides a circuit arrangement having circuit units (101a-101n) which are arranged in a package (100), a connecting device (200) for connecting the circuit units (101a-101n) to one another and for data interchange between the circuit units (101a-101n), and connection units (203) for connecting the circuit units to external circuit units and for supplying electrical power to the circuit arrangement, where data interchange between the circuit units (101a-101n) arranged within the package (100) is performed using electromagnetic waves which are transmitted by transmission units (201a-201n) and are received by reception units (202a-202n). The circuit units (101a-101n) arranged in the package (100) are in this case respectively equipped with the transmission units (201a-201n) and the reception units (202a-202n).

Abstract: An integrated semiconductor memory includes a test mode control circuit and at least one voltage generator for generating an operating voltage that is fed into memory banks via interconnects. Comparator circuits are arranged at locations along the respective interconnects, but preferably at the end of each interconnect. The comparator circuits compare a voltage level on the interconnects with a level of a reference voltage. In a manner dependent on the level comparison, the test mode control circuit generates evaluation signals at contact pads. The reference voltage is fed in via a monitor pad. Using the contact pads, which are generally formed with a large area, the evaluation signals can easily be tapped off by a tester.

Abstract: An integrated semiconductor memory device includes a sense amplifier that is connected to a first bit line via a first output connection and is connected to a second bit line via a second output connection. A memory cell to store a first or a second memory state is connected to the first bit line. When writing/reading the first memory state, the sense amplifier produces a negative voltage at the first output connection and a positive voltage at the second output connection, and when writing/reading the second memory state, it produces the positive voltage at the first output connection and the negative voltage at the second output connection. The production of a negative voltage results in one of the two bit lines being charged approximately to a ground potential during a read or write access.

Abstract: An integrated semiconductor memory device includes a temperature sensor circuit to generate a temperature-dependent control signal, a reference circuit to generate a temperature-independent reference signal, a comparator circuit and a voltage generator circuit. The comparator circuit generates a first level or second level of an activation signal in a manner dependent on the comparison of the control signal and the reference signal which are both fed to it on an input side. The voltage generator circuit generates a first control signal or a second control signal in a manner dependent on the level of the activation signal. The integrated semiconductor memory enables the generation of two control signals for a selection transistor of a memory cell in a manner dependent on whether the temperature sensor circuit detects a temperature in a first temperature range or in a second temperature range.

Abstract: An integrated semiconductor memory operates in synchronization with a clock signal in a normal operating state and is switched from the normal operating state to a test operating state by applying a combination of control signals. During a first test cycle, selection transistors for memory cells are turned on by asynchronously actuating the semiconductor memory using a state change in a control signal. In a second test cycle, the memory content of at least one of the previously activated memory cells is read by synchronously actuating the semiconductor memory using a second signal combination of control signals. By shifting the timing of a signal edge which prompts the state change in the first test cycle close to the time at which the second signal combination is applied in the second test cycle, it is possible to test short reading times which are within one period of the clock signal.

Abstract: A semiconductor arrangement on a semiconductor chip includes a number of lines of a first type that extend outwardly from an inner region toward an outer region of the semiconductor chip. A number of lines of a second type are arranged around the inner region of the semiconductor chip. The lines of the second type are bit lines when the lines of the first type are word lines and the lines of the second type are word lines when the lines of the first type are bit lines. A number of individual element arrays are arranged along the lines of the first type and lines of the second type. The individual element arrays include memory cells.

Abstract: An integrated semiconductor memory includes a test mode control circuit and at least one voltage generator for generating an operating voltage that is fed into memory banks via interconnects. Comparator circuits are arranged at locations along the respective interconnects, but preferably at the end of each interconnect. The comparator circuits compare a voltage level on the interconnects with a level of a reference voltage. In a manner dependent on the level comparison, the test mode control circuit generates evaluation signals at contact pads. The reference voltage is fed in via a monitor pad. Using the contact pads, which are generally formed with a large area, the evaluation signals can easily be tapped off by a tester.

Abstract: A semiconductor memory can have first lines to which memory cells are connected and that run divergently with respect to one another, and second lines to which the memory cells are connected that are curved. Combining the geometry of the memory cell array with storage capacitors laterally offset allows signal delays along word lines and bit lines to be aligned regardless of the position of a memory cell in the memory cell array. The geometry of the memory cell array allows short signal propagation times to be attained particularly along the first lines, which are divergent with respect to one another, this simplifying error-free operation of a semiconductor memory particularly at high clock frequencies.

Abstract: An integrated semiconductor memory device includes a sense amplifier that is connected to a first bit line via a first output connection and is connected to a second bit line via a second output connection. A memory cell to store a first or a second memory state is connected to the first bit line. When writing/reading the first memory state, the sense amplifier produces a negative voltage at the first output connection and a positive voltage at the second output connection, and when writing/reading the second memory state, it produces the positive voltage at the first output connection and the negative voltage at the second output connection. The production of a negative voltage results in one of the two bit lines being charged approximately to a ground potential during a read or write access.

Abstract: A semiconductor arrangement on a semiconductor chip includes a number of lines of a first type that extend outwardly from an inner region toward an outer region of the semiconductor chip. A number of lines of a second type are arranged around the inner region of the semiconductor chip. In one example, the lines of the second type are bit lines when the lines of the first type are word lines and the lines of the second type are word lines when the lines of the first type are bit lines. A number of individual element arrays are arranged along the lines of the first type and lines of the second type. The individual element arrays include memory cells.

Abstract: An integrated semiconductor memory that can be tested includes a control circuit and a memory cell having a selection transistor. In a normal operating mode, the integrated semiconductor memory can be controlled by applying control signals and can be switched from a normal operating mode to a test operating mode by the applying a signal combination of the control signals. In the test operating mode, the control circuit interprets a first of the control signals as a signal for turning off the selection transistor and a second of the control signals or a signal combination of the control signals as a signal for switching the selection transistor into the on state. The method enables the testing of different times between reading a data set into the memory cell and turning off the selection transistor.

Abstract: An integrated semiconductor memory operates in synchronization with a clock signal in a normal operating state and is switched from the normal operating state to a test operating state by applying a combination of control signals. During a first test cycle, selection transistors for memory cells are turned on by asynchronously actuating the semiconductor memory using a state change in a control signal. In a second test cycle, the memory content of at least one of the previously activated memory cells is read by synchronously actuating the semiconductor memory using a second signal combination of control signals. By shifting the timing of a signal edge which prompts the state change in the first test cycle close to the time at which the second signal combination is applied in the second test cycle, it is possible to test short reading times which are within one period of the clock signal.

Abstract: A circuit arrangement for setting a voltage supply for a test mode of an integrated memory contains a voltage generator circuit for generating a supply voltage to apply to bit lines of the memory. A control circuit is driven by a test mode signal for identifying a test mode and is connected to the voltage generator circuit. The control circuit enables the supply voltage to be applied to at least one of the bit lines in the test mode. The voltage generator circuit generates a negative supply voltage value in the test mode in order to carry out a burn-in test mode with a sufficiently high voltage difference between word line and bit line even in the case of small feature dimensions and at the same time to comply with voltage limits with regard to a snapback breakdown.

Abstract: A description is given of a method for the lateral contacting of a semiconductor chip in which, in the case of a first semiconductor chip (11), which has an electrical contact (17) in a side face (14), a layer (27) of an adhesive material (2) is applied to an exposed contact area (17a) and a preformed particle (23) of an electrically conductive material which can be made to melt by supplying heat is applied to the layer (27). A second semiconductor chip (12) is placed against the first semiconductor chip (11) in such a way that the particle (23) adhering to the first semiconductor chip (11) touches an electrical contact (18) of the second semiconductor chip, and both the semiconductor chips (11, 12) and the particle are heated until the particle (23) fuses onto the electrical contacts (17, 18) of the first and second semiconductor chips.

Abstract: An integrated semiconductor memory device includes a temperature sensor circuit to generate a temperature-dependent control signal, a reference circuit to generate a temperature-independent reference signal, a comparator circuit and a voltage generator circuit. The comparator circuit generates a first level or second level of an activation signal in a manner dependent on the comparison of the control signal and the reference signal which are both fed to it on an input side. The voltage generator circuit generates a first control signal or a second control signal in a manner dependent on the level of the activation signal. The integrated semiconductor memory enables the generation of two control signals for a selection transistor of a memory cell in a manner dependent on whether the temperature sensor circuit detects a temperature in a first temperature range or in a second temperature range.

Abstract: An integrated semiconductor memory that can be tested includes a control circuit and a memory cell having a selection transistor. In a normal operating mode, the integrated semiconductor memory can be controlled by applying control signals and can be switched from a normal operating mode to a test operating mode by the applying a signal combination of the control signals. In the test operating mode, the control circuit interprets a first of the control signals as a signal for turning off the selection transistor and a second of the control signals or a signal combination of the control signals as a signal for switching the selection transistor into the on state. The method enables the testing of different times between reading a data set into the memory cell and turning off the selection transistor.

Abstract: An integrated memory contains an access controller for controlling an access for the purpose of reading data from, or writing data to, a memory cell array. The access controller accesses the memory cell array in a first double data rate operating mode of the memory in such a manner that a first data item (which is to be written) of an access cycle is written to the memory cell array with a write latency. In a second single data rate operating mode of the memory, the access controller, in contrast, accesses the memory cell array in such a manner that a first data item of an access cycle is, in contrast, written to the memory cell array in an accelerated manner without the write latency of the first operating mode. This makes it possible to read in data values in an accelerated manner in the second operating mode, in particular a test operating mode.

Abstract: A semiconductor memory has a novel geometry of a memory cell array. Without reducing the distance between storage capacitors that are the most closely adjacent to one another it is possible to structure additional lines between adjacent lines in particular word lines. In a preferred embodiment, the number of word lines required for the number of memory cells remaining the same is reduced, as a result of which word line drivers are saved and substrate area is gained.

Abstract: A circuit arrangement for setting a voltage supply for a test mode of an integrated memory contains a voltage generator circuit for generating a supply voltage to apply to bit lines of the memory. A control circuit is driven by a test mode signal for identifying a test mode and is connected to the voltage generator circuit. The control circuit enables the supply voltage to be applied to at least one of the bit lines in the test mode. The voltage generator circuit generates a negative supply voltage value in the test mode in order to carry out a burn-in test mode with a sufficiently high voltage difference between word line and bit line even in the case of small feature dimensions and at the same time to comply with voltage limits with regard to a snapback breakdown.

Abstract: A description is given of a method for the lateral contacting of a semiconductor chip in which, in the case of a first semiconductor chip (11), which has an electrical contact (17) in a side face (14), a layer (27) of an adhesive material (2) is applied to an exposed contact area (17a) and a preformed particle (23) of an electrically conductive material which can be made to melt by supplying heat is applied to the layer (27). A second semiconductor chip (12) is placed against the first semiconductor chip (11) in such a way that the particle (23) adhering to the first semiconductor chip (11) touches an electrical contact (18) of the second semiconductor chip, and both the semiconductor chips (11, 12) and the particle are heated until the particle (23) fuses onto the electrical contacts (17, 18) of the first and second semiconductor chips.