Patents by Inventor Reiji Mochida
Reiji Mochida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11615299Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.Type: GrantFiled: March 4, 2020Date of Patent: March 28, 2023Assignee: PANASONIC HOLDINGS CORPORATIONInventors: Reiji Mochida, Kazuyuki Kouno, Yuriko Hayata, Takashi Ono, Masayoshi Nakayama
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Patent number: 11604974Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the non-volatile semiconductor memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data.Type: GrantFiled: March 3, 2020Date of Patent: March 14, 2023Assignee: PANASONIC HOLDINGS CORPORATIONInventors: Kazuyuki Kouno, Takashi Ono, Masayoshi Nakayama, Reiji Mochida, Yuriko Hayata
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Patent number: 11495289Abstract: Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.Type: GrantFiled: March 4, 2020Date of Patent: November 8, 2022Assignee: PANASONIC HOLDINGS CORPORATIONInventors: Yuriko Hayata, Kazuyuki Kouno, Masayoshi Nakayama, Reiji Mochida, Takashi Ono, Hitoshi Suwa
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Patent number: 11354569Abstract: A neural network computation circuit includes in-area multiple-word line selection circuits that are provided in one-to-one correspondence to a plurality of word line areas into which a plurality of word lines included in a memory array are logically divided. Each of the in-area multiple-word line selection circuits sets one or more word lines in a selected state or a non-selected state, and includes a first latch and a second latch provided for each word line.Type: GrantFiled: March 2, 2020Date of Patent: June 7, 2022Assignee: PANASONIC CORPORATIONInventors: Masayoshi Nakayama, Kazuyuki Kouno, Yuriko Hayata, Takashi Ono, Reiji Mochida
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Patent number: 11062772Abstract: A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.Type: GrantFiled: December 5, 2018Date of Patent: July 13, 2021Assignee: PANASONIC CORPORATIONInventors: Reiji Mochida, Kazuyuki Kouno, Takashi Ono, Masayoshi Nakayama, Yuriko Hayata
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Publication number: 20210065795Abstract: A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.Type: ApplicationFiled: December 5, 2018Publication date: March 4, 2021Inventors: Reiji MOCHIDA, Kazuyuki KOUNO, Takashi ONO, Masayoshi NAKAYAMA, Yuriko HAYATA
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Publication number: 20200202925Abstract: Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.Type: ApplicationFiled: March 4, 2020Publication date: June 25, 2020Inventors: Yuriko HAYATA, Kazuyuki KOUNO, Masayoshi NAKAYAMA, Reiji MOCHIDA, Takashi ONO, Hitoshi SUWA
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Publication number: 20200202207Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.Type: ApplicationFiled: March 4, 2020Publication date: June 25, 2020Inventors: Reiji MOCHIDA, Kazuyuki KOUNO, Yuriko HAYATA, Takashi ONO, Masayoshi NAKAYAMA
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Publication number: 20200202204Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the non-volatile semiconductor memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data.Type: ApplicationFiled: March 3, 2020Publication date: June 25, 2020Inventors: Kazuyuki KOUNO, Takashi ONO, Masayoshi NAKAYAMA, Reiji MOCHIDA, Yuriko HAYATA
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Publication number: 20200202203Abstract: A neural network computation circuit includes in-area multiple-word line selection circuits that are provided in one-to-one correspondence to a plurality of word line areas into which a plurality of word lines included in a memory array are logically divided. Each of the in-area multiple-word line selection circuits sets one or more word lines in a selected state or a non-selected state, and includes a first latch and a second latch provided for each word line.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventors: Masayoshi NAKAYAMA, Kazuyuki KOUNO, Yuriko HAYATA, Takashi ONO, Reiji MOCHIDA
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Patent number: 10488877Abstract: A regulator circuit has a first non-operating state, a second non-operating state, and an operating state. The regulator circuit includes: a detection circuit that detects a magnitude of an output voltage of the regulator circuit, and outputs a feedback voltage that indicates a result of the detection to a feedback node; an operational amplifier circuit that compares the voltage of the feedback node with a reference voltage, and outputs a voltage that indicates a result of the comparison; and an output circuit that generates the output voltage according to the voltage output from the operational amplifier circuit. A state of the feedback node is different between the first non-operating state and the second non-operating state, and a transition time required to switch from the second non-operating state to the operating state is shorter than a transition time required to switch from the first non-operating state to the operating state.Type: GrantFiled: September 5, 2018Date of Patent: November 26, 2019Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Reiji Mochida, Takashi Ono
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Patent number: 10416694Abstract: A regulator circuit includes: a voltage detection circuit that detects a magnitude of an output voltage of an output node, and outputs a feedback voltage that indicates a result of the detection; an error amplifier circuit that compares the feedback voltage with a reference voltage, and outputs a voltage that indicates a result of the comparison; an output circuit that supplies an output current to the output node according to the voltage output by the error amplifier circuit; a current detection circuit that detects a magnitude of the output current; and a current bias circuit that supplies an output bias current to the output node, and increases or decreases the output bias current based on a result of the detection of the current detection circuit.Type: GrantFiled: September 14, 2018Date of Patent: September 17, 2019Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Takashi Ono, Reiji Mochida
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Publication number: 20190011944Abstract: A regulator circuit includes: a voltage detection circuit that detects a magnitude of an output voltage of an output node, and outputs a feedback voltage that indicates a result of the detection; an error amplifier circuit that compares the feedback voltage with a reference voltage, and outputs a voltage that indicates a result of the comparison; an output circuit that supplies an output current to the output node according to the voltage output by the error amplifier circuit; a current detection circuit that detects a magnitude of the output current; and a current bias circuit that supplies an output bias current to the output node, and increases or decreases the output bias current based on a result of the detection of the current detection circuit.Type: ApplicationFiled: September 14, 2018Publication date: January 10, 2019Inventors: Takashi ONO, Reiji MOCHIDA
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Publication number: 20190004554Abstract: A regulator circuit has a first non-operating state, a second non-operating state, and an operating state. The regulator circuit includes: a detection circuit that detects a magnitude of an output voltage of the regulator circuit, and outputs a feedback voltage that indicates a result of the detection to a feedback node; an operational amplifier circuit that compares the voltage of the feedback node with a reference voltage, and outputs a voltage that indicates a result of the comparison; and an output circuit that generates the output voltage according to the voltage output from the operational amplifier circuit. A state of the feedback node is different between the first non-operating state and the second non-operating state, and a transition time required to switch from the second non-operating state to the operating state is shorter than a transition time required to switch from the first non-operating state to the operating state.Type: ApplicationFiled: September 5, 2018Publication date: January 3, 2019Inventors: Reiji MOCHIDA, Takashi ONO
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Patent number: 9747979Abstract: A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.Type: GrantFiled: August 13, 2015Date of Patent: August 29, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Masayoshi Nakayama, Kazuyuki Kouno, Reiji Mochida, Keita Takahashi
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Patent number: 9478283Abstract: A nonvolatile semiconductor memory device includes: a memory cell (MC0) including a cell transistor (TC0) and a variable resistance element (RR0); a memory cell (MC1) including a cell transistor (TC1) and a variable resistance element (RR1); a word line (WL0) connected to the cell transistor (TC0); a word line (WL1) connected to the cell transistor (TC1); a data line (SL0) connecting the cell transistor (TC0) and the variable resistance element (RR1) to each other; and a data line (BL0) connecting the variable resistance element (RR0) and the cell transistor (TC1) to each other.Type: GrantFiled: November 19, 2013Date of Patent: October 25, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Reiji Mochida, Kazuyuki Kouno
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Publication number: 20150348626Abstract: A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Masayoshi NAKAYAMA, Kazuyuki KOUNO, Reiji MOCHIDA, Keita TAKAHASHI
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Publication number: 20150279457Abstract: A nonvolatile semiconductor memory device includes: a memory cell (MC0) including a cell transistor (TC0) and a variable resistance element (RR0); a memory cell (MC1) including a cell transistor (TC1) and a variable resistance element (RR1); a word line (WL0) connected to the cell transistor (TC0); a word line (WL1) connected to the cell transistor (TC1); a data line (SL0) connecting the cell transistor (TC0) and the variable resistance element (RR1) to each other; and a data line (BL0) connecting the variable resistance element (RR0) and the cell transistor (TC1) to each other.Type: ApplicationFiled: November 19, 2013Publication date: October 1, 2015Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Reiji Mochida, Kazuyuki Kouno
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Patent number: 8711629Abstract: Bit lines connected to each nonvolatile memory cell are selected by corresponding selective transistors. A first drive circuit for driving the gate of one of the selective transistors receives a voltage selected by a first voltage switch, and a second drive circuit for driving the gate of the other selective transistor receives a voltage selected by a second voltage switch. A transistor constituting the first drive circuit is different in structure from a transistor constituting the second drive circuit.Type: GrantFiled: September 10, 2012Date of Patent: April 29, 2014Assignee: Panasonic CorporationInventors: Masayoshi Nakayama, Takashi Ono, Reiji Mochida
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Patent number: 8593888Abstract: In a semiconductor memory device, the output of a regulator is coupled to the inputs of first and second switches, the output of the first switch is coupled to a path for supplying the drain voltage of a memory cell in the first mode, and the output of the second switch is coupled to a path for supplying the gate voltage of the memory cell in the second mode. A fourth switch is placed in parallel with the second switch: the output of the fourth switch is coupled to the output of the second switch, to supply the gate voltage of the memory cell in the first mode. Thus, one regulator is used as both the regulator for the drain voltage of the memory cell and the regulator for the gate voltage of the memory cell.Type: GrantFiled: August 22, 2012Date of Patent: November 26, 2013Assignee: Panasonic CorporationInventors: Reiji Mochida, Takafumi Maruyama, Yukimasa Hamamoto