Abstract: According to one embodiment, a memory device includes a pillar extending in a first direction through a first, second, and third conductive layers. The pillar includes ferroelectric layer. A first transistor is at an intersection of the pillar and the first conductive layer. A second transistor is at an intersection of the pillar and the second conductive layer. A ferroelectric memory cell is at an intersection with the third conductive layer and the pillar. A circuit supplies a read pulse to the memory cell in a read sequence. The read pulse has a first voltage value in a first period and has a second voltage value with the same polarity as the first voltage value in a second period after the first period. The second voltage value is lower than the first.

Abstract: A semiconductor memory device according to an embodiment includes a stacked body in which a gate electrode layer and a first insulating layer are alternately stacked in a first direction, a semiconductor layer in the stacked body and extending in the first direction, a second insulating layer between the semiconductor layer and the stacked body, a third insulating layer provided between the second insulating layer and the stacked body, and a first layer between the second insulating layer and the third insulating layer. The first layer contains silicon and nitrogen and includes a first region between the gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, the first region contains or does not contain fluorine, the second region contains fluorine, and a fluorine concentration of the second region is higher than a fluorine concentration of the first region.

Abstract: A semiconductor memory device includes a semiconductor layer, a gate electrode, a gate insulating film disposed therebetween, first and second wirings connected to the semiconductor layer, and a third wiring connected to the gate electrode and is configured to execute a write operation, an erase operation, and a read operation. In the write operation, a write voltage of a first polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the erase operation, an erase voltage of a second polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the read operation, the write voltage or a voltage having a larger amplitude than that of the write voltage is supplied between the third wiring and at least one of the first wiring or the second wiring.

Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

Abstract: A semiconductor memory device includes a semiconductor layer, a gate electrode, a gate insulating film disposed therebetween, first and second wirings connected to the semiconductor layer, and a third wiring connected to the gate electrode and is configured to execute a write operation, an erase operation, and a read operation. In the write operation, a write voltage of a first polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the erase operation, an erase voltage of a second polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the read operation, the write voltage or a voltage having a larger amplitude than that of the write voltage is supplied between the third wiring and at least one of the first wiring or the second wiring.

Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

Abstract: A semiconductor memory device of an embodiment includes: a semiconductor layer; a gate electrode layer; a first insulating layer provided between the semiconductor layer and the gate electrode layer; a second insulating layer provided between the first insulating layer and the gate electrode layer; and an intermediate layer provided between the first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number 61), a space group P42/nmc (space group number 137), or a space group R-3m (space group number 166), and the intermediate layer containing hafnium (Hf), oxygen (O), and nitrogen (N).

Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.

Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.

Abstract: A semiconductor memory device of an embodiment includes: a semiconductor layer; a gate electrode layer; a first insulating layer provided between the semiconductor layer and the gate electrode layer; a second insulating layer provided between the first insulating layer and the gate electrode layer; and an intermediate layer provided between the first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number 61), a space group P42/nmc (space group number 137), or a space group R-3m (space group number 166), and the intermediate layer containing hafnium (Hf), oxygen (O), and nitrogen (N).

Abstract: A storage device includes a substrate, first wirings arranged in a first direction and extending in a second direction, second wirings arranged in the second direction and extending in the first direction, resistance portions between the first and second wirings, third wirings between the second wirings and the substrate, arranged in the second direction and extending in a third direction, semiconductor portions each connected to second and third wirings, a fourth wiring extending in the second direction and facing the semiconductor portions, insulating portions between the semiconductor portions and the fourth wiring, and a contact connected to each first wiring. The semiconductor portions include a first portion and a second portion closer to the contact, and a length in the second direction of an insulating portion between the first portion and the fourth wiring is greater than that of another insulating portion between the second portion and the fourth wiring.

Abstract: A storage device includes a substrate, first wirings arranged in a first direction and extending in a second direction, second wirings arranged in the second direction and extending in the first direction, resistance portions between the first and second wirings, third wirings between the second wirings and the substrate, arranged in the second direction and extending in a third direction, semiconductor portions each connected to second and third wirings, a fourth wiring extending in the second direction and facing the semiconductor portions, insulating portions between the semiconductor portions and the fourth wiring, and a contact connected to each first wiring. The semiconductor portions include a first portion and a second portion closer to the contact, and a length in the second direction of an insulating portion between the first portion and the fourth wiring is greater than that of another insulating portion between the second portion and the fourth wiring.