Patents by Inventor Reiko Hiruta

Reiko Hiruta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9147579
    Abstract: A method of manufacturing a semiconductor device with an SON structure having a thick cavity inside a semiconductor substrate is disclosed. The method forms a plurality of trenches with a predetermined distance between adjacent trenches. Each trench has, at a middle portion between the trench top and bottom, an outwardly expanding sectional shape. High temperature annealing is conducted driving surface migration of silicon atoms in the surface region of the silicon substrate to close the top of the trench, resulting in formation of a plurality of small cavities composed of the trenches in the silicon substrate. Further high temperature annealing joins the plurality of small cavities to form a single cavity. Second opening width x2 at the middle portion ranges from 1.1 times to 1.5 times of first opening width x1 at the top of the trench. Aspect ratio of the trench is at least 8.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 29, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Reiko Hiruta
  • Publication number: 20140061868
    Abstract: A method of manufacturing a semiconductor device with an SON structure having a thick cavity inside a semiconductor substrate is disclosed. The method forms a plurality of trenches with a predetermined distance between adjacent trenches. Each trench has, at a middle portion between the trench top and bottom, an outwardly expanding sectional shape. High temperature annealing is conducted driving surface migration of silicon atoms in the surface region of the silicon substrate to close the top of the trench, resulting in formation of a plurality of small cavities composed of the trenches in the silicon substrate. Further high temperature annealing joins the plurality of small cavities to form a single cavity. Second opening width x2 at the middle portion ranges from 1.1 times to 1.5 times of first opening width x1 at the top of the trench. Aspect ratio of the trench is at least 8.
    Type: Application
    Filed: July 17, 2013
    Publication date: March 6, 2014
    Inventor: Reiko HIRUTA
  • Patent number: 7947600
    Abstract: A micro-transformer manufacturing method is provided, which can improve throughput, prevent a crack from entering an insulating film between coils, and manufacture the micro-transformer without using a mask material having a high selection ratio. An insulating film is deposited on the whole face of a semiconductor substrate having an impurity-diffused region. This insulating film is partially removed to form a first opening and a second opening. A primary coil is formed such that a center pad contacts the impurity-diffused region through the first opening. A thin insulating film is deposited on the primary coil. An insulator material having a secondary coil formed thereon is adhered onto the insulating film on the primary coil by adhesive tape. The insulator material is sized to not cover both a pad, connected with the center pad of the primary coil through the impurity-diffused region, and an outer-end pad of the primary coil.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: May 24, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Masanobu Iwaya, Reiko Hiruta, Katsunori Ueno, Kunio Mochizuki
  • Publication number: 20090280646
    Abstract: A micro-transformer manufacturing method is provided, which can improve throughput, prevent a crack from entering an insulating film between coils, and manufacture the micro-transformer without using a mask material having a high selection ratio. An insulating film is deposited on the whole face of a semiconductor substrate having an impurity-diffused region. This insulating film is partially removed to form a first opening and a second opening. A primary coil is formed such that a center pad contacts the impurity-diffused region through the first opening. A thin insulating film is deposited on the primary coil. An insulator material having a secondary coil formed thereon is adhered onto the insulating film on the primary coil by adhesive tape. The insulator material is sized to not cover both a pad, connected with the center pad of the primary coil through the impurity-diffused region, and an outer-end pad of the primary coil.
    Type: Application
    Filed: April 24, 2008
    Publication date: November 12, 2009
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Masanobu IWAYA, Reiko HIRUTA, Katsunori UENO, Kunio MOCHIZUKI
  • Patent number: 7368363
    Abstract: A method of manufacturing a semiconductor device includes the steps of: exposing a semiconductor surface of a substrate; annealing the substrate in a hydrogen atmosphere at a hydrogen pressure between 200 Torr and 760 Torr and a temperature between 1000° C. and 1050° C. to planarize the exposed semiconductor surface; and forming a gate insulator film on the planarized semiconductor surface.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: May 6, 2008
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Reiko Hiruta, Hitoshi Kuribayashi, Ryosuke Shimizu
  • Publication number: 20050106794
    Abstract: A semiconductor substrate is annealed after forming a trench in a semiconductor substrate and prior to forming a gate insulator film, at an annealing temperature T between 980° C. and 1150° C. in an atmosphere of a gas mixture containing a rare gas and hydrogen, in which the content of hydrogen is 1.3×10?18 exp(0.043T) % or lower in volume, to planarize the side wall of the trench and to round the corners of the trench at the curvature of 0.003 nm?1 or smaller. Alternatively, a semiconductor substrate with a trench formed therein is annealed prior to forming a gate insulator film, at an annealing temperature T between 980° C. and 1040° C. in an atmosphere of a gas mixture containing a rare gas and hydrogen, in which the content of hydrogen is 6.11×10?14 exp(0.0337T) % or higher in volume, to planarize the side wall of the trench but so as not to round the corners of the trench such that the curvature thereof is 0.006 nm?1 or higher.
    Type: Application
    Filed: September 20, 2004
    Publication date: May 19, 2005
    Inventors: Hitoshi Kuribayashi, Reiko Hiruta, Ryosuke Shimizu
  • Publication number: 20050106847
    Abstract: A method of manufacturing a semiconductor device includes the steps of: exposing a semiconductor surface of a substrate; annealing the substrate in a hydrogen atmosphere at a hydrogen pressure between 200 Torr and 760 Torr and a temperature between 1000° C. and 1050° C. to planarize the exposed semiconductor surface; and forming a gate insulator film on the planarized semiconductor surface.
    Type: Application
    Filed: November 8, 2004
    Publication date: May 19, 2005
    Inventors: Reiko Hiruta, Hitoshi Kuribayashi, Ryosuke Shimizu