Patents by Inventor Reiko Nojima

Reiko Nojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7230554
    Abstract: The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: June 12, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Takeuchi, Masami Murakata, Masaaki Yamada, Reiko Nojima, Takashi Ishioka, Mutsunori Igarashi
  • Publication number: 20060197695
    Abstract: The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive.
    Type: Application
    Filed: April 26, 2006
    Publication date: September 7, 2006
    Inventors: Hideki Takeuchi, Masami Murakata, Masaaki Yamada, Reiko Nojima, Takashi Ishioka, Mutsunori Igarashi
  • Patent number: 7064691
    Abstract: A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: June 20, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Takeuchi, Masami Murakata, Masaaki Yamada, Reiko Nojima, Takashi Ishioka, Mutsunori Igarashi
  • Publication number: 20040043048
    Abstract: Disclosed herein are (1) cosmetic made with silver type anti-microbial water soluble glass in oily cosmetic composition of the cosmetic, and (2) a process for producing the cosmetic that is highly effective against bacteria and fungi, and that is safer to the skin. The cosmetic is characterized by letting silver type anti-microbial water soluble glass in oily cosmetic composition release slowly from oil phase of the cosmetic to the water phase of the cosmetic only when anti-bacterial agent contact with water in the cosmetic.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 4, 2004
    Applicants: Ishizuka Garasu Kabushiki Kaisha, SHIN-EI CHEMICAL CO., LTD., Cosmo Trends Corporation
    Inventors: Makio Nomura, Reiko Nojima, Togo Murata
  • Publication number: 20030011500
    Abstract: The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive.
    Type: Application
    Filed: August 7, 2002
    Publication date: January 16, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideki Takeuchi, Masami Murakata, Masaaki Yamada, Reiko Nojima, Takashi Ishioka, Mutsunori Igarashi
  • Patent number: 6459331
    Abstract: A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: October 1, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Takeuchi, Masami Murakata, Masaaki Yamada, Reiko Nojima, Takashi Ishioka, Mutsunori Igarashi
  • Patent number: 6058257
    Abstract: In a semiconductor integrated circuit comprising: a logic circuit which performs prescribed logical operations; first power supply lines (fundamental power lines) which supply source power to the logic circuit; and second power supply lines which are provided, on the logic circuit, in a wiring level different from that for the first power supply lines and also which are interconnected with the first power supply lines through contact holes at the intersections therebetween, the number and the positions of the contact holes can be determined so as to minimize the voltage drop value at the logic circuit. As a result, the voltage drop can be relaxed, thus assuring stable operations of the circuit.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: May 2, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Reiko Nojima
  • Patent number: 5974244
    Abstract: A layout pattern generation method and device executing this method in which a symbolic layout of a semiconductor integrated circuit is generated, the sizes of transistors are changed by using the circuit connection information of the layout pattern, the correspondence information of the transistors whose sizes have been changed are generated by using the symbolic layout and the changed circuit connection information, the symbolic layout after the transistor sizes have been changed is generated by using the correspondence information, the generated symbolic layout is compacted, and then a new layout pattern is generated by using the compacted layout pattern.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: October 26, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sachio Hayashi, Reiko Nojima