Patents by Inventor Reiko SHAMOTO

Reiko SHAMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11849586
    Abstract: A semiconductor device is provided, including: a substrate; a first stacked portion including a plurality of first electrode layers stacked in a first direction via a first insulator; a second stacked portion provided above the first stacked portion and including a plurality of second electrode layers stacked in the first direction via a second insulator; a connection portion provided between the first stacked portion and the second stacked portion, and including a third insulator; a column-shaped portion extending in the first stacked portion, the second stacked portion, and the connection portion in the first direction, and including a semiconductor body and a charge storage portion; and a semiconductor pillar provided between the substrate and the column-shaped portion, and in contact with the substrate and the semiconductor body of the column-shaped portion.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: December 19, 2023
    Assignee: Kioxia Corporation
    Inventors: Kaito Shirai, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
  • Publication number: 20230027173
    Abstract: A semiconductor device is provided, including: a substrate; a first stacked portion including a plurality of first electrode layers stacked in a first direction via a first insulator; a second stacked portion provided above the first stacked portion and including a plurality of second electrode layers stacked in the first direction via a second insulator; a connection portion provided between the first stacked portion and the second stacked portion, and including a third insulator; a column-shaped portion extending in the first stacked portion, the second stacked portion, and the connection portion in the first direction, and including a semiconductor body and a charge storage portion; and a semiconductor pillar provided between the substrate and the column-shaped portion, and in contact with the substrate and the semiconductor body of the column-shaped portion.
    Type: Application
    Filed: October 3, 2022
    Publication date: January 26, 2023
    Applicant: Kioxia Corporation
    Inventors: Kaito SHIRAI, Hideto TAKEKIDA, Tatsuo IZUMI, Reiko SHAMOTO, Takahisa KANEMURA, Shigeo KONDO
  • Patent number: 11502100
    Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: November 15, 2022
    Assignee: Kioxia Corporation
    Inventors: Kaito Shirai, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
  • Patent number: 11031415
    Abstract: According to one embodiment, in a semiconductor storage device, a peripheral circuit supplies a first voltage to a second region when supplying a select potential to a region corresponding to the second region, in a second conductive layer. The peripheral circuit supplies a second voltage higher than the first voltage to a first region when supplying a select potential to a region corresponding to the first region, in the second conductive layer.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoichi Minemura, Michiaki Matsuo, Reiko Shamoto
  • Publication number: 20200403000
    Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kaito SHIRAI, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
  • Patent number: 10804290
    Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kaito Shirai, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
  • Publication number: 20200303404
    Abstract: According to one embodiment, in a semiconductor storage device, a peripheral circuit supplies a first voltage to a second region when supplying a select potential to a region corresponding to the second region, in a second conductive layer. The peripheral circuit supplies a second voltage higher than the first voltage to a first region when supplying a select potential to a region corresponding to the first region, in the second conductive layer.
    Type: Application
    Filed: September 4, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yoichi MINEMURA, Michiaki MATSUO, Reiko SHAMOTO
  • Publication number: 20190214405
    Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kaito SHIRAI, Hideto Takekida, Tatsuo Izumi, Reiko Shamoto, Takahisa Kanemura, Shigeo Kondo
  • Patent number: 9837264
    Abstract: A nonvolatile semiconductor memory device comprises: a substrate; a memory cell that is disposed on the substrate and accumulates a charge as data; and a cover layer covering the memory cell. The cover layer has a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a memory cell side.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Reiko Shamoto, Hideto Takekida
  • Publication number: 20170018558
    Abstract: A nonvolatile semiconductor memory device comprises: a substrate; a memory cell that is disposed on the substrate and accumulates a charge as data; and a cover layer covering the memory cell. The cover layer has a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a memory cell side.
    Type: Application
    Filed: March 18, 2016
    Publication date: January 19, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Reiko SHAMOTO, Hideto Takekida