Abstract: An apparatus comprises at least one processor to execute software processes, a memory system to store data for access by the at least one processor, and checkpointing circuitry to trigger saving, to the memory system, of checkpoints of context state associated with at least one software process executed by the at least one processor. The saving of checkpoints is a background process performed by the checkpointing circuitry in the background of execution of the software processes by the at least one processor.

Abstract: Methods and systems for detecting errors when performing a convolutional operation is provided. Predicted checksum data, corresponding to input checksum data and kernel checksum data, is obtained. The convolutional operation is performed to obtain an output feature map. Output checksum data is generated and the predicted checksum data and the output checksum data are compared, the comparing taking account of partial predicted checksum data configured to correct for a lack of padding when performing the convolution operation, wherein the partial predicted checksum data corresponds to input checksum data for a subset of the values in the input feature map and kernel checksum data for a subset of the values in the kernel.

Abstract: An apparatus comprises at least one processor to execute software processes, a memory system to store data for access by the at least one processor, and checkpointing circuitry to trigger saving, to the memory system, of checkpoints of context state associated with at least one software process executed by the at least one processor. The saving of checkpoints is a background process performed by the checkpointing circuitry in the background of execution of the software processes by the at least one processor.

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

Abstract: A system, apparatus and method for accessing an electronic storage medium, such as a memory location storing a page table, or range table. A virtual address of the electronic storage medium is identified that corresponds to designated portions, such as a range of addresses of the electronic storage medium. The virtual address is translated to a corresponding physical address and one or more commands are identified as being excluded from execution in the designated portions of the electronic storage medium. This may be accomplished by using a routine such as mprotect( ). A fault indication, or decoration, is provided to meta-data associated with the physical address, which is associated with the designated portions of the electronic storage medium when excluded commands are provided to the physical address. A mechanism, such as hardware, is actuated when the fault is generated.

Abstract: A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

Abstract: A system, apparatus and method for accessing an electronic storage medium, such as a memory location storing a page table, or range table. A virtual address of the electronic storage medium is identified that corresponds to designated portions, such as a range of addresses of the electronic storage medium. The virtual address is translated to a corresponding physical address and one or more commands are identified as being excluded from execution in the designated portions of the electronic storage medium. This may be accomplished by using a routine such as mprotect( ). A fault indication, or decoration, is provided to meta-data associated with the physical address, which is associated with the designated portions of the electronic storage medium when excluded commands are provided to the physical address. A mechanism, such as hardware, is actuated when the fault is generated.

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

Abstract: A coarse-grained reconfigurable array includes a processing element array, instruction memory circuitry, data memory circuitry, and an instruction fetch unit. The processing element array includes a number of processing elements. The instruction memory circuitry is coupled to the processing element array and configured to store a set of instructions. During each one of a number of processing cycles, the instruction memory circuitry provides instructions from the set of instructions to the processing elements. The instruction fetch unit is coupled to the processing element array and the instruction memory circuitry and configured to receive a result of a conditional instruction evaluated by one of the processing elements and provide the instruction fetch signals based at least in part on the result of the conditional instruction such that only instructions associated with a correct branch of the conditional instruction are provided to the plurality of processing elements.

Abstract: A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.

Abstract: An apparatus is provided comprising receiving circuitry to receive a representation of a circuit comprising a plurality of flops. Categorisation circuitry determines data dependencies between the flops from the representation and generates a categorisation of the flops into one of at least: a vulnerable category, a conditional category, and an isolated category, in dependence on the data dependencies. The categorisation indicates the vulnerability of the flops to transient errors. Output circuitry outputs the categorisation of the flops. The conditional category comprises those of the flops whose change in value is indicated by a change in a value in a corresponding flop in the flops or corresponding signal.

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.