Abstract: The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure (240) over a substrate (210), the gate structure (240) including a gate electrode (248) located over a nitrided gate dielectric (243), and forming a nitrided region (310) over a sidewall of the nitrided gate dielectric (243).

Abstract: The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure (240) over a substrate (210), the gate structure (240) including a gate electrode (248) located over a nitrided gate dielectric (243), and forming a nitrided region (310) over a sidewall of the nitrided gate dielectric (243).

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer over a substrate in a first active region and a second active region of a semiconductor device, patterning the silicon oxide masking layer to expose the substrate in the first active region. The method further includes forming a layer of dielectric material over the substrate in the first active region, the patterned silicon oxide masking layer protecting the substrate from the layer of dielectric material in the second active region.

Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a masking layer over a semiconductor substrate in a first active region and a second active region of a semiconductor device, patterning the masking layer to expose the semiconductor substrate in the first active region, and subjecting exposed portions of the semiconductor substrate to a nitrogen containing plasma, thereby forming a first layer of gate dielectric material over the semiconductor substrate in the first active region.

Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region.

Abstract: A method of forming a narrow feature, such as a gate electrode (14) in an integrated circuit is disclosed. A gate layer (14) such as polycrystalline silicon is disposed near a surface of a substrate (12), and a hardmask layer (16) is formed over the gate layer (14). The hardmask layer (16) includes one or more dielectric layers (16a, 16b, 16c) such as silicon-rich silicon nitride, silicon oxynitride, and oxide. Photoresist (18) sensitive to 193 nm UV light is patterned over the hardmask layer (16) to define a feature of a first width (CD) that is reliably patterned at that wavelength. The hardmask layer (16) is then etched to clear from the surface of the gate layer (14). A timed overetch of the hardmask layer (16) reduces hardmask CD and that of the overlying photoresist (18) to the desired feature size. Etch of the gate layer is then carried out to form the desired feature.

Abstract: According to one embodiment of the invention, a method for manufacturing a transistor is provided. The method includes masking a polysilicon layer of a semiconductor device to have a dimension greater than a critical dimension of a gate to be formed. The polysilicon layer overlies a substrate layer. The method also includes incompletely etching the polysilicon layer. The method also includes forming a source region and a drain region in the substrate layer through the incompletely etched polysilicon layer by doping the substrate layer and applying heat at a first temperature. The method also includes forming a source extension and a drain extension in the substrate layer after forming the source region and the drain region by doping the substrate layer and applying heat at a second temperature.

Abstract: A method of forming a narrow feature, such as a gate electrode (14) in an integrated circuit is disclosed. A gate layer (14) such as polycrystalline silicon is disposed near a surface of a substrate (12), and a hardmask layer (16) is formed over the gate layer (14). The hardmask layer (16) includes one or more dielectric layers (16a, 16b, 16c) such as silicon-rich silicon nitride, silicon oxynitride, and oxide. Photoresist (18) sensitive to 193 nm UV light is patterned over the hardmask layer (16) to define a feature of a first width (CD) that is reliably patterned at that wavelength. The hardmask layer (16) is then etched to clear from the surface of the gate layer (14). A timed overetch of the hardmask layer (16) reduces hardmask CD and that of the overlying photoresist (18) to the desired feature size. Etch of the gate layer is then carried out to form the desired feature.

Abstract: A method for dynamically controlling a semiconductor manufacturing process for producing a semiconductor component includes performing a plurality of process segments. Each respective process segment is performed for a respective processing interval. The method includes the steps of: (a) determining a relationship among respective process intervals for at least two particular process segments of the plurality of process segments; (b) determining a first respective process interval required for a first particular process segment to effect a desired result in the semiconductor component; and (c) using the relationship to establish the respective process interval required for at least one selected particular process segment in order to fix the respective process interval for a controlled process segment other than the at least one selected particular process segment.

Abstract: A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.

Abstract: The present invention relates to a method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.

Abstract: A plasma process is described which produces an undamaged and uncontaminated silicon surface by consuming silicon by continuous oxidation through a surface oxide layer and a simultaneous etch of the exposed silicon oxide surface. The surface silicon dioxide layer thickness is controlled as an equilibrium between oxide growth from oxygen atoms reaching the silicon surface and etching of the oxide surface. The silicon dioxide protects the silicon surface from plasma damage and from contamination.