Patents by Inventor Reina Nishino
Reina Nishino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11899573Abstract: A memory system includes a memory and a controller. The memory is configured to store a number of valid data in each of a plurality of logical blocks and a number of valid data for each of a plurality of banks in each of the logical blocks. The controller is configured to: select logical blocks of garbage collection target candidates based on the numbers of valid data in the logical blocks; calculate a maximum value among the numbers of valid data for the banks in each of the logical blocks of the garbage collection target candidates as a respective comparison value; and select one of the logical blocks of the garbage collection targets based on comparing the respective comparison values of the logical blocks of the garbage collection target candidates with each other.Type: GrantFiled: March 2, 2022Date of Patent: February 13, 2024Assignee: KIOXIA CORPORATIONInventors: Reina Nishino, Tetsuya Sunata, Takumi Fujimori
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Publication number: 20230089083Abstract: A memory system includes a memory and a controller. The memory is configured to store a number of valid data in each of a plurality of logical blocks and a number of valid data for each of a plurality of banks in each of the logical blocks. The controller is configured to: select logical blocks of garbage collection target candidates based on the numbers of valid data in the logical blocks; calculate a maximum value among the numbers of valid data for the banks in each of the logical blocks of the garbage collection target candidates as a respective comparison value; and select one of the logical blocks of the garbage collection targets based on comparing the respective comparison values of the logical blocks of the garbage collection target candidates with each other.Type: ApplicationFiled: March 2, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventors: Reina NISHINO, Tetsuya SUNATA, Takumi FUJIMORI
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Patent number: 10776007Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.Type: GrantFiled: November 11, 2015Date of Patent: September 15, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Atsushi Kunimatsu, Masaki Miyagawa, Hiroshi Nozue, Kazuhiro Kawagome, Hiroto Nakai, Hiroyuki Sakamoto, Tsutomu Owa, Tsutomu Unesaki, Reina Nishino, Kenichi Maeda, Mari Takada
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Patent number: 10467020Abstract: According to one embodiment, the memory device includes a non-volatile memory, a volatile memory, and a controller. The controller carries out the transition to two different sleep states depending on a sleep instruction from the host device and saves sleep state information indicating the sleep state after the transition to the host-side storage device. Upon receiving a return instruction from the host device, the controller carries out return processing in accordance with the sleep state information stored in the host-side storage device.Type: GrantFiled: September 2, 2016Date of Patent: November 5, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuji Izumi, Kenichi Maeda, Kenji Funaoka, Reina Nishino, Toshio Fujisawa, Nobuhiro Kondo
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Patent number: 10146483Abstract: According to one embodiment, a memory system is connectable to a host including a first memory. The memory system includes a non-volatile second memory, a volatile third memory, and a controller. The controller uses the third memory as a work memory, and executes data transfer between the host and the second memory. The controller receives a first command to change a power mode from the host. The controller transfers first data to the first memory and transfers second data to the second memory in response to the receipt of the first command. The controller transmits a response of completion of data transfer. The first data and the second data are included in third data. The third data is data in the third memory.Type: GrantFiled: September 1, 2016Date of Patent: December 4, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Reina Nishino, Kenichi Maeda, Kenji Funaoka, Nobuhiro Kondo, Toshio Fujisawa
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Publication number: 20170249102Abstract: According to one embodiment, an information processing apparatus includes a host device, a memory system and a power supply circuit. The host device includes a volatile first memory and a first control circuit. The memory system includes a non-volatile second memory in which user data is stored and a second control circuit. The second control circuit executes transfer of the user data between the host device and the second memory. The first memory includes an area used by the second control circuit. The second control circuit uses the area as a buffer for the transfer. The first control circuit causes the power supply circuit to start and stop the power supply to the memory system. The first control circuit accesses, while the power supply to the memory system is stopped, the buffer.Type: ApplicationFiled: September 7, 2016Publication date: August 31, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi MAEDA, Kenji FUNAOKA, Reina NISHINO, Nobuhiro KONDO, Toshio FUJISAWA
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Publication number: 20170249247Abstract: According to one embodiment, a memory system is connectable to a host including a first memory. The memory system includes a non-volatile second memory, a volatile third memory, and a controller. The controller uses the third memory as a work memory, and executes data transfer between the host and the second memory. The controller receives a first command to change a power mode from the host. The controller transfers first data to the first memory and transfers second data to the second memory in response to the receipt of the first command. The controller transmits a response of completion of data transfer. The first data and the second data are included in third data. The third data is data in the third memory.Type: ApplicationFiled: September 1, 2016Publication date: August 31, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Reina NISHINO, Kenichi MAEDA, Kenji FUNAOKA, Nobuhiro KONDO, Toshio FUJISAWA
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Publication number: 20170249167Abstract: According to one embodiment, the memory device includes a non-volatile memory, a volatile memory, and a controller. The controller carries out the transition to two different sleep states depending on a sleep instruction from the host device and saves sleep state information indicating the sleep state after the transition to the host-side storage device. Upon receiving a return instruction from the host device, the controller carries out return processing in accordance with the sleep state information stored in the host-side storage device.Type: ApplicationFiled: September 2, 2016Publication date: August 31, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yuji IZUMI, Kenichi MAEDA, Kenji FUNAOKA, Reina NISHINO, Toshio FUJISAWA, Nobuhiro KONDO
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Publication number: 20160062660Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.Type: ApplicationFiled: November 11, 2015Publication date: March 3, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi KUNIMATSU, Masaki MIYAGAWA, Hiroshi NOZUE, Kazuhiro KAWAGOME, Hiroto NAKAI, Hiroyuki SAKAMOTO, Tsutomu OWA, Tsutomu UNESAKI, Reina NISHINO, Kenichi MAEDA, Mari TAKADA
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Publication number: 20130198437Abstract: In an embodiment, a device includes a first unit, a second unit, and a third unit. The first unit generates a write address representing a write position to sequentially store sequential data from a processor to a nonvolatile main memory. The second unit generates order information representing a degree of newness of write. The third unit writes sequentially writes the sequential data at the write address with the order information.Type: ApplicationFiled: July 27, 2012Publication date: August 1, 2013Inventors: Takashi OMIZO, Tsutomu OWA, Atsushi KUNIMATSU, Hiroto NAKAI, Masaki MIYAGAWA, Reina NISHINO, Hiroyuki SAKAMOTO
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Publication number: 20120191900Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.Type: ApplicationFiled: January 17, 2012Publication date: July 26, 2012Inventors: Atsushi KUNIMATSU, Masaki MIYAGAWA, Hiroshi NOZUE, Kazuhiro KAWAGOME, Hiroto NAKAI, Hiroyuki SAKAMOTO, Tsutomu OWA, Tsutomu UNESAKI, Reina NISHINO, Kenichi MAEDA, Mari TAKADA
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Publication number: 20120030413Abstract: According to one embodiment, a memory management device configured to manage a main memory including a nonvolatile semiconductor memory, the memory management device includes a sort module configured to sort, at a time of a data write operation in the nonvolatile semiconductor memory, data to write areas of the nonvolatile semiconductor memory, based on information of a frequency of write which is determined by a data attribute of the data, and a control module configured to write the sorted data in the nonvolatile semiconductor memory by an incremental-write type.Type: ApplicationFiled: March 17, 2011Publication date: February 2, 2012Inventors: Masaki Miyagawa, Atsushi Kunimatsu, Tsutomu Owa, Reina Nishino