Abstract: An interconnect structure includes a first metallization layer, a second metallization layer, and a via metallization layer connecting the first metallization layer to the second metallization layer. The via metallization layer includes a metal via having a first portion extending in a first direction and a second portion extending from the first portion in a second direction different than the first direction.

Abstract: A semiconductor structure is provided that includes a device layer and a non-perpendicular (or non-orthogonal) wiring layer that includes a skip-level via that connects this wiring level to the device layer. The skip-level via passes through another wiring layer that is positioned between the non-perpendicular wiring layer and the device layer, without physically contacting any metal lines that are present in this another wiring layer.

Abstract: Embodiments of the invention include an isolation layer under a nanosheet stack of a transistor and a graded layer under the isolation layer. The graded layer includes an impurity gradient.

Abstract: A vertical transport field effect transistor (VTFET) apparatus includes a fin-shaped channel structure; a gate stack that surrounds the channel structure; a top source/drain structure at a top end of the channel structure; a top interconnect layer above the top source/drain structure; a top contact that electrically connects the top source/drain structure to the top interconnect layer; a bottom source/drain structure at a bottom end of the channel structure; a backside interconnect layer below the bottom source/drain structure; and a backside contact that touches a bottom surface of the bottom source/drain structure and also touches a side surface of the bottom source/drain structure and electrically connects the bottom source/drain structure to the backside interconnect layer.

Abstract: Embodiments of the invention include a transistor comprising a gate region and a source/drain region. A first isolation layer is under the gate region. A second isolation layer is separated from the first isolation layer by a third isolation layer.

Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring separated into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment and a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring. A distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.

Abstract: Semiconductor device and methods of forming the same include a semiconductor channel. A top source/drain structure is on the semiconductor channel. A bottom source/drain structure is under the semiconductor channel. The bottom source/drain structure includes a doped semiconductor part and a conductor part, with the conductor part covering a bottom surface of the doped semiconductor part.

Abstract: A VTFET is provided on a wafer. A backside power delivery network is on a backside of the wafer. A first backside contact is connected to a bottom source/drain region of the VTFET and a first portion of the backside power delivery network. A second backside contact is connected to top source/drain region of the VTFET and a second portion of the backside power delivery network.

Abstract: A method for forming a semiconductor device includes forming a front side of the semiconductor device, the front side comprising a metal wire M2, and a plurality of power rails coupled to the M2. Further, the method includes forming a through silicon via (TSV) from a back side of the semiconductor device to the front side, the TSV connecting a first power rail of the front side with a metal wire M1 on the back side. Further, the method includes forming a power delivery network on the back side, the TSV providing power from the power delivery network to the front side.

Abstract: A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.

Abstract: An interconnect structure includes a first metal layer comprising at least one metal wire with a first segment and a local extension having a width in a first direction that is larger than a width of the first segment. A second metal layer is on top or below the first metal layer comprising at least one metal wire. A via is connected between the at least one metal wire of the first metal layer and the at least one metal wire of the second metal layer.

Abstract: A vertical-transport field-effect transistor (VTFET) is on a wafer. The VTFET has a first width. The first width is a contacted poly pitch (CPP). A bottom source/drain region of the VTFET extends at least the first width from the VTFET. A contact from a frontside of the VTFET is connected to the bottom source/drain region.

Abstract: A semiconductor device including an interleaved/nested structure of subtractive interconnects and damascene interconnects. The semiconductor device includes a subtractive-etched interconnect wiring level having subtractive interconnects and a damascene interconnect wiring level having damascene interconnects. The subtractive-etched interconnect wiring level includes first electrodes that have a first potential second electrodes that have a second potential different from the first potential, with the second electrodes generated to interleave the first electrodes. The semiconductor also includes a damascene interconnect wiring level that includes other first electrodes having the first potential, and other second electrodes having the second potential. In the damascene interconnect wiring level, the other second electrodes are also interleaved by the other first electrodes.

Abstract: A semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.

Abstract: An interconnect structure for connecting an upper wiring line to a lower wiring line includes a via connecting a lower portion of the upper wiring line with an upper surface of the lower wiring line and a wrap-around via portion formed integrally with the via, the wrap-around portion extending along and electrically contacting a portion of the sides of the lower wiring line.

Abstract: A skip-level via structure is provided that electrically connects a third level of interconnect wiring to a first level of interconnect wiring or a fourth level of interconnect wiring to a first level of interconnect wiring. In the first instance, the skip-level via structure enables connection even when the first level of interconnect wiring and the third level of interconnect wiring do not line up. In the second instance, the skip-level via structure enables a low resistance connection of the fourth level of interconnect wiring to the first level of interconnect wiring due to increased contact area.

Abstract: A semiconductor structure comprises a vertical transistor, a first contact connecting to a source/drain region at a first side of the vertical transistor, a second contact extending from the first side of the vertical transistor to a second side of the vertical transistor, and an interconnect structure at the first side of the vertical transistor connecting the first contact to the second contact.

Abstract: A semiconductor apparatus includes a substrate; a first conductive feature disposed on the substrate, the first conductive feature comprising a conductive material; a second conductive feature disposed on the substrate, the second conductive feature comprising the conductive material; a dielectric material at least partially surrounding the first conductive feature and the second conductive feature; and an interconnect between the first conductive feature and the second conductive feature, the interconnect comprising the conductive material integral with the first conductive feature and the second conductive feature and extending through the dielectric material and below the first conductive feature and the second conductive feature.