Abstract: A fin-shaped field effect transistor (finFET) device comprising includes a substrate. an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.

Abstract: Multi-voltage threshold vertical transport transistors and methods of fabrication generally include forming the transistors with vertically oriented silicon fin channels for both the n-type doped field effect transistors (nFET) and the p-type doped field effect transistors (pFET). A silicon oxynitride interfacial layer is provided on sidewalls of the fins in the nFET and a silicon dioxide interfacial with aluminum is provided on sidewalls of the fins in the pFET to provide an aluminum induced dipole. A high k dielectric overlays the interfacial layers and a common work function metal overlays the high k dielectric layer to define a gate structure.

Abstract: A method is presented for mitigating conductance drift in intercalation cells for neuromorphic computing. The method includes forming a first electro-chemical random access memory (ECRAM) structure over a substrate and forming a second ECRAM over the substrate, the first and second ECRAMs sharing a common contact. The common contact can be either a source contact or a drain contact. Each of the first and second ECRAMs can include a tungsten oxide layer, an electrolyte layer, and a gate contact.

Abstract: A stacked resistive random access memory (ReRAM) structure is provided. The stacked ReRAM structure includes a channel, a ReRAM cell sub-structure and a contact via sub-structure. The ReRAM cell structure includes ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel. The contact via sub-structures includes first, second, third and fourth contact vias, which are separate from one another. The first contact via is disposed in exclusive operative contact with the ReRAM cell layer. The second contact via is disposed in exclusive operative contact with the drain layer. The third contact via is disposed in exclusive operative contact with the gate layer. The fourth contact via is disposed in exclusive operative contact with the source layer.

Abstract: A test probe assembly for use in testing a semiconductor wafer includes a probe card, a plurality of test probes mounted to the probe card and one or more piezoelectric elements mounted to each test probe. The piezoelectric elements are configured to move respective probe ends of the individual test probes in at least one direction to facilitate realignment of the probe ends for semiconductor wafer testing.

Abstract: A stacked resistive random access memory (ReRAM) structure is provided. The stacked ReRAM structure includes a channel, a ReRAM cell sub-structure and a contact via sub-structure. The ReRAM cell structure includes ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel. The contact via sub-structures includes first, second, third and fourth contact vias, which are separate from one another. The first contact via is disposed in exclusive operative contact with the ReRAM cell layer. The second contact via is disposed in exclusive operative contact with the drain layer. The third contact via is disposed in exclusive operative contact with the gate layer. The fourth contact via is disposed in exclusive operative contact with the source layer.

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

Abstract: Vertically stacked memory devices and methods of manufacture are provided. The structures include a substrate stack including a first row of horizontal electrodes disposed over a first insulating layer and first insulating layer disposed over a substrate. The substrate stack further includes a second row of horizontal electrodes separated from the first row of horizontal electrodes by a second insulating layer, and the first row of horizontal electrodes is form over and substantially parallel to the second row of horizontal electrodes. A third insulating layer is formed over the second row of horizontal electrodes. A plurality of vertical gate trenches formed through the third insulating layer, the second row of horizontal electrodes, the second insulating layer, the first row of horizontal electrodes and the first insulating layer. The plurality of vertical gate trenches filled with a layer of channel material, a layer of electrolyte material and filled with a metal.

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.

Abstract: Integrated chips include a semiconductor fin that has a first active region and a second active region that are electrically separated by an oxide region that completely penetrates the semiconductor fin. A first semiconductor device is formed on the first active region. A second semiconductor device formed on the second active region.

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer. A semiconductor device is formed on each of the active regions.

Abstract: Provided are embodiments of a multi-task learning system with hardware acceleration that includes a resistive random access memory crossbar array. Aspects of the invention includes an input layer that has one or more input layer nodes for performing one or more tasks of the multi-task learning system, a hidden layer that has one or more hidden layer nodes, and a shared hidden layer that has one or more shared hidden layer nodes which represent a parameter, wherein the shared hidden layer nodes are coupled to each of the one or more hidden layer nodes of the hidden layer.

Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.

Abstract: A test probe assembly for determining the integrity of a test pad of a semiconductor wafer. The test probe assembly includes a probe card, a plurality of test probes mounted to the probe card, a fiber optic lead mounted to each test probe and arranged to direct incident light toward individual test pads of the semiconductor wafer and a plurality of photodetectors arranged about the probe card. Individual photodetectors are configured to receive light reflected off a dielectric coating of the test pad corresponding to a first set of light rays emitted by the test pad and configured to receive light reflected off a metallic base of the test pad corresponding to a second set of light rays emitted by the test pad, and to generate first and second output signals associated with the first and second sets of light rays to create image data of the individual test pads.

Abstract: A test probe assembly includes a probe card, a plurality of test probes mounted to the probe card with each of the test probes having a probe tip segment and a probe end for positioning adjacent respective individual test pads of a semiconductor wafer, and a fiber optic lead mounted to each test probe. The fiber optic leads are arranged to direct incident light toward respective individual test pads of the semiconductor wafer. A plurality of photodetectors may be arranged about the probe card with individual photodetectors configured for reception of light reflected off the respective individual test pads to emit output signals used to generate image data representative of the individual test pads on the semiconductor wafer. The image data may be utilized to align the test pads with the test probes for subsequent testing.