Patents by Inventor Reinaldo Ariel Vega
Reinaldo Ariel Vega has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11139299Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.Type: GrantFiled: June 18, 2019Date of Patent: October 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ravikumar Ramachandran, Reinaldo Ariel Vega
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Patent number: 11056391Abstract: A method and a semiconductor device includes a substrate, and a first device type formed on the substrate, the first device type including an active channel region including a first fin, the first fin including a first fin width which is narrower than a second fin width above and below the active channel region. A second device type can be formed on the same substrate, the second device type includes a second active channel region including a second fin, the second fin including a first fin width which is the same as the second fin width both above and below the second active channel region.Type: GrantFiled: June 30, 2016Date of Patent: July 6, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hari V. Mallela, Robert Russell Robison, Reinaldo Ariel Vega, Rajasekhar Venigalla
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Patent number: 10896976Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.Type: GrantFiled: August 15, 2019Date of Patent: January 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
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Patent number: 10559690Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.Type: GrantFiled: August 9, 2017Date of Patent: February 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
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Publication number: 20190371941Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.Type: ApplicationFiled: August 15, 2019Publication date: December 5, 2019Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, REINALDO ARIEL VEGA
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Publication number: 20190304980Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.Type: ApplicationFiled: June 18, 2019Publication date: October 3, 2019Inventors: Ravikumar Ramachandran, Reinaldo Ariel Vega
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Patent number: 10403628Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.Type: GrantFiled: December 23, 2014Date of Patent: September 3, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ravikumar Ramachandran, Reinaldo Ariel Vega
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Publication number: 20190252548Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.Type: ApplicationFiled: August 9, 2017Publication date: August 15, 2019Applicant: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
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Publication number: 20190051751Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.Type: ApplicationFiled: August 9, 2017Publication date: February 14, 2019Applicant: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
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Publication number: 20180006118Abstract: A method and a semiconductor device includes a substrate, and a first device type formed on the substrate, the first device type including an active channel region including a first fin, the first fin including a first fin width which is narrower than a second fin width above and below the active channel region. A second device type can be formed on the same substrate, the second device type includes a second active channel region including a second fin, the second fin including a first fin width which is the same as the second fin width both above and below the second active channel region.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Hari V. Mallela, Robert Russell Robison, Reinaldo Ariel Vega, Rajasekhar Venigalla
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Patent number: 9818877Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.Type: GrantFiled: September 18, 2014Date of Patent: November 14, 2017Assignee: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
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Patent number: 9530684Abstract: Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.Type: GrantFiled: June 3, 2016Date of Patent: December 27, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Emre Alptekin, Viraj Yashawant Sardesai, Cung Do Tran, Reinaldo Ariel Vega
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Publication number: 20160284586Abstract: Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.Type: ApplicationFiled: June 3, 2016Publication date: September 29, 2016Inventors: Emre ALPTEKIN, Viraj Yashawant SARDESAI, Cung Do TRAN, Reinaldo Ariel VEGA
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Publication number: 20160260833Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.Type: ApplicationFiled: September 18, 2014Publication date: September 8, 2016Applicant: lnternational Business Machines CorporationInventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
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Publication number: 20160181250Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Applicant: International Business Machines CorporationInventors: Ravikumar Ramachandran, Reinaldo Ariel Vega
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Patent number: 9368493Abstract: Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.Type: GrantFiled: July 8, 2014Date of Patent: June 14, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Emre Alptekin, Viraj Yashawant Sardesai, Cung Do Tran, Reinaldo Ariel Vega
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Publication number: 20160013184Abstract: Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.Type: ApplicationFiled: July 8, 2014Publication date: January 14, 2016Inventors: Emre Alptekin, Viraj Yashawant Sardesai, Cung Do Tran, Reinaldo Ariel Vega
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Publication number: 20150129939Abstract: Embodiments of the present invention provide an improved structure and method for forming high aspect ratio contacts. A horizontally formed contact etch stop layer is deposited in a narrow area where a contact is to be formed. A gas cluster ion beam (GCIB) process is used in the deposition of the horizontally formed contact etch stop layer.Type: ApplicationFiled: November 11, 2013Publication date: May 14, 2015Applicant: International Business Machines CorporationInventors: Emre Alptekin, Viraj Yashawant Sardesai, Reinaldo Ariel Vega
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Patent number: 8652914Abstract: An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.Type: GrantFiled: March 3, 2011Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Emre Alptekin, Sameer Hemchand Jain, Reinaldo Ariel Vega
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Patent number: 8415250Abstract: A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.Type: GrantFiled: April 29, 2011Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Emre Alptekin, Dong-Ick Lee, Viraj Yashawant Sardesai, Cung Do Tran, Jian Yu, Reinaldo Ariel Vega, Rajasekhar Venigalla