Abstract: A memory system includes a memory that provides digital data and a built-in self-test (BIST) circuit for testing the memory for determining defective storage units of the memory. The memory system has a data output for providing data from the memory to an external system. The data output of the memory system has a first bit width. The memory has a data output that has a second bit width that is greater than the first bit width. The BIST circuit has a data input that is of the second bit width.

Abstract: Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.

Abstract: In a system on chip (SOC) device, continuity of a memory repair signature chain, which is accessible by all enabled memory systems, is provided, even when certain memory systems are gated (off) for certain SOC configurations. A mechanism for converting between compressed and uncompressed memory repair data within the repair chain is provided so that memory systems that support either uncompressed memory repair data (such as ternary content addressable memories) or compressed memory repair data can be incorporated in the SOC.

Abstract: A content addressable memory (CAM) and methods of operating a CAM are provided. The method for operating a CAM includes: during a first mode, performing a search function in a CAM bit array, the search result output at a match port of the CAM bit array; and during a second mode, columnwise reading data in the CAM bit array, the read column data output at the match data port of the CAM bit array. The method may include writing the CAM bit array with a predetermined data pattern. The method may further include providing an indication of pass/fail based upon comparing the read column data with expected data.

Abstract: A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory.

Abstract: In a system on chip (SOC) device, continuity of a memory repair signature chain, which is accessible by all enabled memory systems, is provided, even when certain memory systems are gated (off) for certain SOC configurations. A mechanism for converting between compressed and uncompressed memory repair data within the repair chain is provided so that memory systems that support either uncompressed memory repair data (such as ternary content addressable memories) or compressed memory repair data can be incorporated in the SOC.

Abstract: A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory.

Abstract: Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.