Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiments can select a wide-bus in the IC design. Next, the embodiments can divide the wide-bus into one or more subsets of bus-wires, wherein each subset of bus-wires corresponds to a unit of information. The embodiments can then optimize clock gating for each subset of bus-wires.

Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiments can select a wide-bus in the IC design. Next, the embodiments can divide the wide-bus into one or more subsets of bus-wires, wherein each subset of bus-wires corresponds to a unit of information. The embodiments can then optimize clock gating for each subset of bus-wires.

Abstract: Behavioral synthesis allows a circuit design to be specified in a high-level hardware description language (HLHDL) that is more oriented towards expressing the desired behavior than the underlying hardware mechanisms by which such behavior will be accomplished. The present invention permits behavioral synthesis to be accomplished with control chaining information, but with the control chaining information determined by a basic data-flow based pretiming. Control chaining is useful because it permits advanced scheduling techniques in which the computation of a conditional functional unit can be considered for scheduling in the same clock cycle as the functional units that depend on the evaluation of that conditional functional unit. The present invention speeds up the step of pretiming, responsible for determining control chaining information, by eliminating additional processing, beyond data-flow chaining, for determining control chaining ready times.