Abstract: An EPROM-like memory includes a substrate having a source region, a drain region, and a channel. The memory includes a gate stack formed by a gate oxide, a storage electrode, a second gate oxide and a gate electrode. The gate oxide is configured on the substrate above the channel. The storage electrode is configured on the gate oxide. The second gate oxide is configured on the storage electrode. The gate electrode is configured on the second gate oxide. The memory includes an interspace that is configured between the drain region and the storage electrode. The interspace is filled with a gas or contains a vacuum. The memory includes an outer spacing web that is configured laterally beside the gate stack. The outer spacing web is also configured on the drain region. The outer spacing web is made of doped polycrystalline silicon.

Abstract: The fabrication method results in a stacked capacitor, in particular for use in a semiconductor memory device. The stacked capacitor has a semiconductor substrate of a first conductivity type and a well of a second conductivity type formed in the substrate. A stack of alternating first conductive layers of the first conductivity type and second conductive layers of the second conductivity type, with the interposition of respective insulation layers are formed on the semiconductor substrate. Two neighboring insulation layers are connected to one another on a first side of the stack by insulation bridges in such a way as to provide continuous insulation of the second conductive layers toward the first side. A first spacer, which is provided on the first side of the stack, forms a first capacitor connection and is preferably connected to the semiconductor substrate and to the first conductive layers.