Abstract: A monolithically integrable semiconductor circuit having an input section into which respective electrical signals which are to be evaluated and which have been provided by groups of binary pulses are serially feedable, includes a clock-controlled shift register in the input section, the shift register being operable by shift pulses from the controlling clock thereof. The shift register has a plurality of register cells corresponding in number at least to the number of binary digits of the groups of binary pulses. The semiconductor circuit also includes a logic circuit, at least two of the register cells having an output operatively connected to the logic circuit for controlling the logic circuit.