Abstract: A method for manufacturing a device on a substrate includes forming a layer structure on the substrate, forming an auxiliary layer on the layer structure, forming a planarization layer on the auxiliary layer and on the substrate, exposing the auxiliary layer by a chemical mechanical polishing process and removing at least partly the auxiliary layer to form a planar surface of the remaining auxiliary layer or of the layer structure and the planarization layer. The chemical mechanical polishing process has a first removal rate with respect to the planarization layer and a second removal rate with respect to the auxiliary layer and the first removal rate is greater than the second removal rate.

Abstract: A method for manufacturing a device on a substrate includes forming a layer structure on the substrate, forming an auxiliary layer on the layer structure, forming a planarization layer on the auxiliary layer and on the substrate, exposing the auxiliary layer by a chemical mechanical polishing process and removing at least partly the auxiliary layer to form a planar surface of the remaining auxiliary layer or of the layer structure and the planarization layer. The chemical mechanical polishing process has a first removal rate with respect to the planarization layer and a second removal rate with respect to the auxiliary layer and the first removal rate is greater than the second removal rate.

Abstract: An integrated circuit includes a substrate. A surface region of the substrate includes a contact pad region. A passivation layer stack includes at least one passivation layer. The passivation layer stack is formed over the surface region and adjacent to the contact pad region. An upper portion of the passivation layer stack is removed in, in a portion of the passivation layer stack proximate the contact pad region.

Abstract: A method for manufacturing a device on a substrate includes forming a layer structure on the substrate, forming an auxiliary layer on the layer structure, forming a planarization layer on the auxiliary layer and on the substrate, exposing the auxiliary layer by a chemical mechanical polishing process and removing at least partly the auxiliary layer to form a planar surface of the remaining auxiliary layer or of the layer structure and the planarization layer. The chemical mechanical polishing process has a first removal rate with respect to the planarization layer and a second removal rate with respect to the auxiliary layer and the first removal rate is greater than the second removal rate.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first conductive layer over a substrate. The first conductive layer has a top surface and sidewalls, wherein the first conductive layer comprises an overhang of a non-conductive material along the sidewalls. The method further includes forming an insulating layer on the first conductive layer, and forming a sacrificial layer over the insulating layer and the overhang of the first conductive layer. The sacrificial layer is partially removed wherein a residue of the sacrificial layer remains beneath the overhang, and a second conductive layer is formed on the insulating layer.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first conductive layer over a substrate. The first conductive layer has a top surface and sidewalls, wherein the first conductive layer comprises an overhang of a non-conductive material along the sidewalls. The method further includes forming an insulating layer on the first conductive layer, and forming a sacrificial layer over the insulating layer and the overhang of the first conductive layer. The sacrificial layer is partially removed wherein a residue of the sacrificial layer remains beneath the overhang, and a second conductive layer is formed on the insulating layer.

Abstract: An integrated circuit includes a substrate. A surface region of the substrate includes a contact pad region. A passivation layer stack includes at least one passivation layer. The passivation layer stack is formed over the surface region and adjacent to the contact pad region. An upper portion of the passivation layer stack is removed in, in a portion of the passivation layer stack proximate the contact pad region.

Abstract: In a method of processing a contact pad, a passivation layer stack including at least one passivation layer is formed on at least an upper surface of a contact pad region. A first portion of the passivation layer stack is removed from above the contact pad region, wherein a second portion of the passivation layer remains on the contact pad region and covers the contact pad region. An adhesion layer is formed on the passivation layer stack. The adhesion layer is patterned, wherein the adhesion layer is removed from above the contact pad region. Furthermore, the second portion of the passivation layer stack is removed.

Abstract: A method for manufacturing a device on a substrate includes forming a layer structure on the substrate, forming an auxiliary layer on the layer structure, forming a planarization layer on the auxiliary layer and on the substrate, exposing the auxiliary layer by a chemical mechanical polishing process and removing at least partly the auxiliary layer to form a planar surface of the remaining auxiliary layer or of the layer structure and the planarization layer. The chemical mechanical polishing process has a first removal rate with respect to the planarization layer and a second removal rate with respect to the auxiliary layer and the first removal rate is greater than the second removal rate.

Abstract: A method for producing an integrated circuit including a fuse element, a fuse-memory element or a resistor element is disclosed. In one embodiment, at least one metallization layer is applied onto a substrate. A hard mask is applied onto the at least one metallization layer. The at least one metallization layer is wet chemically etched by using the hard mask and the fuse element. The fuse-memory element or the resistor element is formed in a region in which the at least one metallization layer has been etched.

Abstract: In a method of processing a contact pad, a passivation layer stack including at least one passivation layer is formed on at least an upper surface of a contact pad region. A first portion of the passivation layer stack is removed from above the contact pad region, wherein a second portion of the passivation layer remains on the contact pad region and covers the contact pad region. An adhesion layer is formed on the passivation layer stack. The adhesion layer is patterned, wherein the adhesion layer is removed from above the contact pad region. Furthermore, the second portion of the passivation layer stack is removed.

Abstract: The document explains, inter alia, a method in which a titanium nitride layer is removed by wet chemical means (106). Following removal of the titanium nitride, further metalization strata are produced (114). The result is an integrated circuit arrangement having connections which have a low electrical resistance. The circuit arrangement is particularly suitable for the purpose of switching high powers.

Abstract: A method for producing an integrated circuit including a fuse element, a fuse-memory element or a resistor element is disclosed. In one embodiment, at least one metallization layer is applied onto a substrate. A hard mask is applied onto the at least one metallization layer. The at least one metallization layer is wet chemically etched by using the hard mask and the fuse element. The fuse-memory element or the resistor element is formed in a region in which the at least one metallization layer has been etched.

Abstract: An electronic component is described and has a dielectric layer which is constructed on a substrate, conductive surfaces that are constructed on the dielectric layer, and an electrically conductive guard structure. The guard structure is disposed in a plane above the conductive surfaces such that the conductive surfaces are not completely covered by the guard structure.