Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d?(8/25)x+142 ?m, where x is a pitch of the second contact pads in micrometers.

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d?(8/25)x+142 ?m, where x is a pitch of the second contact pads in micrometers.

Abstract: A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d?(8/25)x+142 ?m, wherein x is the pitch of the second contact pads in micrometers.

Abstract: The present invention relates to a process for the purification of a contaminant-containing stream by bringing the stream to be purified into contact with a heterogeneous photocatalyst with irradiation with light, where the bringing into contact takes place in the presence of at least one compound dissolved in the stream and comprising at least one metal selected from the group consisting of iron, chromium, nickel, cobalt, manganese and mixtures thereof, and to the use of a heterogeneous photocatalyst for the purification of a contaminant-containing stream, where, in the stream to be purified, at least one compound comprising at least one metal selected from the group consisting of iron, chromium, nickel, cobalt, manganese and mixtures thereof is present in dissolved form.

Abstract: A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d?(8/25)x+142 ?m, wherein x is the pitch of the second contact pads in micrometers.

Abstract: The present invention relates to a method of purifying wastewater by contacting the wastewater which is to be purified with a rod-shaped TiO2 photocatalyst which has a BET surface area of 25 to 200 m2/g, a pore volume of 0.10 to 1.00 ml/g, and a median pore diameter of 0.005 to 0.050 ?m, with irradiation by light, and to the use of such a rod-shaped TiO2 photocatalyst which has a BET surface area of 25 to 200 m2/g, a pore volume of 0.10 to 1.00 ml/g, and a median pore diameter of 0.005 to 0.050 ?m, for purifying wastewater with irradiation by light.

Abstract: A process for preparing an organometallic framework material comprising reacting at least one metal salt with at least one at least bidentate compound capable of coordination to the metal ion of said metal salt, in the presence of an aqueous solvent system and at least one base wherein at least one bidentate compound comprises at least carboxy group and at least one further group which is not a carboxy group and which is capable of forming a hydrogen bridge linkage.

Abstract: A process for preparing an organometallic framework material comprising reacting at least one metal salt with at least one at least bidentate compound capable of coordination to the metal ion of said metal salt, in the presence of an aqueous solvent system and at least one base wherein at least one bidentate compound comprises at least carboxy group and at least one further group which is not a carboxy group and which is capable of forming a hydrogen bridge linkage.

Abstract: The present invention relates to a container for uptaking, or storing, or releasing, or uptaking and storing, or uptaking and releasing, or storing and releasing, or uptaking, storing and releasing at least one gas, comprising at least one opening for allowing the at least one gas to enter and exit or at least one opening for allowing the at least one gas to enter and at least one opening for allowing the at least one gas to exit said container, and a gas-tight mechanism capable of storing the at least one gas under a pressure of from greater than 45 to 750 bar inside the container, said container further comprising a metallo-organic framework material comprising pores and at least one metal ion and at least one at least bidentate organic compound which is bound to said metal ion, as well as to a fuel cell comprising said container, and to a method of using said container or said fuel cell for supplying power to power plants, cars, trucks, busses, cell phones, and laptops.