Abstract: A wide ROM-PROM memory is structured of multiple memory chips in parallel plus an auxiliary parity memory chip to hold parity bits for each corresponding addressable location in each memory chip. Sensing means is provided to check parity of data bits read from each memory location to verify integrity of the read-out.

Abstract: A parity detection scheme for a wide memory structure of RAM memory chips provides an auxiliary RAM parity memory chip to store parity data for each corresponding input line of each memory chip corresponding for each address of each memory chip. This parity data is compared to comparable parity data which is read-out of any corresponding address of each of said memory chips.

Abstract: A parity checking system for establishing integrity of data transfer on a wide bus. Each set of "4" bus lines of a multiple line bus is passed from a driver chip to a corresponding receiver chip. An added parity driver chip senses each corresponding bit line of each driver chip to develop a set of four parity signals for comparison with corresponding parity signals from each corresponding bit line of each one of a set of receiver chips. Any discrepancy will generate a parity error signal.

Abstract: A data processing system having a plurality of processors and a plurality of dedicated and shared memory modules. Each processor includes a cache for speeding up data transfers between the processor and its dedicated memory and also between the processor and one or more shared memories. The integrity of the data in each cache with respect to the shared memory modules is maintained by providing each shared memory with a cache monitoring and control capability which monitors processor reading and writing requests and, in response to this monitoring, maintains an accurate, updatable record of the data addresses in each cache while also providing for invalidating data in a cache when it is no longer valid.

Abstract: A transmission system is disclosed for transmitting asynchronous binary signals from a source to a selected utilization device without requiring a system clock common to the source and utilization device. The system includes apparatus for converting the asynchronous binary signals into complementary pairs for transmission to respective electronic devices. Each electronic device is capable of transmitting a complementary pair applied thereto to the utilization device while also being responsive to applied 1, 1 inputs from a strobe circuit to prevent transmission to the utilization device when such transmission is to be prevented. A presence detecting circuit responsive to the outputs of the electronic devices detects when all of the data bits have arrived and initiates operation of the utilization means in response thereto.