Abstract: A bipolar semiconductor memory has a matrix of word-by-word selectable memory cells and selective circuits associated therewith in the word direction and in the bit direction for selective memory words in response to receipt of address signals. A decoder includes output switches in the form of emitter followers which are connected to respective word lines. The memory cells present capacitive loads to the lines and a recharging circuit is connected to each word line of the matrix and includes a common constant current source which is connected to each word line by way of a respective coupling element. Each of the coupling elements are embodied as base-emitter paths of recharge transistors which have the respective collectors connected directly to a respective word line. A base resistance is also connected between the respective word line and the bae of a recharge transistor.