Abstract: An electronic device and method is disclosed. In one example, the electronic device includes an electrically insulating material, a first load electrode arranged on a first surface of the electrically insulating material, and a second load electrode arranged on a second surface of the electrically insulating material opposite to the first surface, wherein the load electrodes are separated by the electrically insulating material along the entire length on which the load electrodes have opposite sections, wherein surfaces of the load electrodes facing away from the electrically insulating material are uncovered by the electrically insulating material.

Abstract: An electronic device and method is disclosed. In one example, the electronic device includes an electrically insulating material, a first load electrode arranged on a first surface of the electrically insulating material, and a second load electrode arranged on a second surface of the electrically insulating material opposite to the first surface, wherein the load electrodes are separated by the electrically insulating material along the entire length on which the load electrodes have opposite sections, wherein surfaces of the load electrodes facing away from the electrically insulating material are uncovered by the electrically insulating material.

Abstract: A power semiconductor module arrangement includes a semiconductor substrate having first and second metallization layers attached to a dielectric insulation layer, the dielectric insulation layer being disposed between the metallization layers. A layer of heat-conducting material is arranged between the semiconductor substrate and a base plate in a vertical direction of the power semiconductor module arrangement. The layer of heat-conducting material is arranged adjacent to a plane surface of the semiconductor substrate and adjacent to a plane surface of the base plate. The semiconductor substrate has a first thermal expansion coefficient of 8 ppm/K or lower, the base plate has a second thermal expansion coefficient of 9 ppm/K or lower, and the layer of heat-conducting material has a third thermal expansion coefficient of 18 ppm/K or higher. The layer of heat-conducting material has a thickness in the vertical direction of between 40 ?m and 150 ?m.

Abstract: A power semiconductor module arrangement includes a semiconductor substrate having first and second metallization layers attached to a dielectric insulation layer, the dielectric insulation layer being disposed between the metallization layers. A layer of heat-conducting material is arranged between the semiconductor substrate and a base plate in a vertical direction of the power semiconductor module arrangement. The layer of heat-conducting material is arranged adjacent to a plane surface of the semiconductor substrate and adjacent to a plane surface of the base plate. The semiconductor substrate has a first thermal expansion coefficient of 8 ppm/K or lower, the base plate has a second thermal expansion coefficient of 9 ppm/K or lower, and the layer of heat-conducting material has a third thermal expansion coefficient of 18 ppm/K or higher. The layer of heat-conducting material has a thickness in the vertical direction of between 40 ?m and 150 ?m.

Abstract: One aspect relates to a method for producing an electronic module assembly. According to the method, a curable first mass extending between a substrate assembly and a module housing is cured while a circuit carrier of the substrate assembly has at least a first temperature. Between a side wall of the module housing and the substrate assembly, an adhesive connection is formed by curing a curable second mass. Subsequent to curing the first mass, the circuit carrier is cooled down to below a second temperature lower than the first temperature. Embodiments of the electronic module assembly are also described.

Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.

Abstract: Power semiconductor packages described herein each include a substrate having two or more metal layers and one or more insulating layers for separating the metal layers. The substrate insulating layers are formed from a polymer material to reduce the CTE mismatch between the substrate metal layers and the substrate insulating layers.

Abstract: A circuit arrangement includes a power semiconductor circuit, a first charge storage unit and a second charge storage unit. The first charge storage unit has first and second terminals, the second charge storage unit has first and second terminals, and the power semiconductor circuit has first and second terminals. The power semiconductor circuit also has a first semiconductor component and a second semiconductor component, the load paths of which are electrically connected in series between the first and second terminals of the power semiconductor circuit. A first connection electrically connects the first terminal of the first charge storage unit to the first terminal of the second charge storage unit, and a second connection electrically connects the second terminal of the first charge storage unit to the second terminal of the second charge storage unit. A magnetic core is electromagnetically coupled to the first and/or second connections.

Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.

Abstract: One or more additional sense terminals are added to discrete semiconductor packages, assemblies and semiconductor modules, including power semiconductor modules, to sense accurately the voltage between the gate and emitter/source of voltage-controlled chips, inside the package, assembly or module.

Abstract: A semiconductor package is described which meets a plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package includes a semiconductor die embedded in or covered by a molded plastic body, the molded plastic body satisfying only a subset of the plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package further includes a plurality of terminals protruding from the molded plastic body and electrically connected to the semiconductor die, and a coating applied to at least part of the molded plastic body and/or part of the plurality of terminals. The coating satisfies each predetermined electrical, mechanical, chemical and/or environmental requirement not satisfied by the molded plastic body.

Abstract: One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The semiconductor chip is disposed in the module housing. A dielectric first encapsulation is disposed in the module housing, in physical contact with both the semiconductor chip and the substrate and has a first modulus of elasticity. A dielectric second encapsulation is disposed in the module housing and has a second modulus of elasticity. The first encapsulation is a polymer and disposed between the substrate and the second encapsulation. The semiconductor chip is disposed between the first encapsulation and the substrate. Further, the first modulus of elasticity is greater than the second modulus of elasticity.

Abstract: A semiconductor module includes a base plate having an inner region adjacent an edge region, a substrate attached to the inner region of the base plate and a heat sink on which the base plate is mounted so that the base plate is interposed between the substrate and the heat sink and at least part of the inner region of the base plate contacts the heat sink. The module further includes a stress relief mechanism configured to permit the base plate to bend away from the heat sink in the edge region responsive to a thermal load so that at least part of the inner region of the base plate remains in contact with the heat sink.

Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.

Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.

Abstract: A transistor is driven by a drive circuit that includes a logic unit and drive signal generator. The drive signal generator outputs a temporally variable drive voltage for driving the transistor, based on setpoint state information. A short-circuit information signal contains information about a possible short circuit of a load connected in series with the transistor load path. In response to this signal, the drive signal generator switches on the transistor at a first point in time by setting the transistor drive voltage to a value or a value range above a switch-on threshold value of the transistor, but limits the drive voltage to a maximum first switch-on voltage limit value. The drive signal generator maintains the drive voltage at maximally the first switch-on voltage limit value or sets the drive voltage to a value or a value range greater than or equal to a second switch-on voltage limit value.

Abstract: One or more additional sense terminals are added to discrete semiconductor packages, assemblies and semiconductor modules, including power semiconductor modules, to sense accurately the voltage between the gate and emitter/source of voltage-controlled chips, inside the package, assembly or module.

Abstract: A multiplicity of power semiconductor switching elements of the same type parallel have a load current terminal for a load current input and a load current terminal for a load current output. At least one outer load current terminal and at least one inner load current terminal per load current direction include a load current input and a load current output. At least one contacting device for common electrical contacting all of the load current terminals of the same load current direction includes a load current input and a load current output. The contacting device includes a plurality of terminal tongues which are respectively fastened on an associated load current terminal. The geometry and/or profile of the terminal tongue of an outer load current terminal differs from the geometry and/or profile of the terminal tongue of an inner load current terminal of the same contacting device.

Abstract: A semiconductor module is produced by providing a circuit carrier having a metallization, an electrically conductive wire and a bonding device. With the aid of the bonding device, a bonding connection is produced between the metallization and a first section of the wire. A separating location and a second section of the wire, the second section being spaced apart from the separating location, are defined on the wire. The wire is reshaped in the second section. Before or after reshaping, the wire is severed at the separating location, such that a terminal conductor of the semiconductor module is formed from a part of the wire. The terminal conductor is bonded to the metallization and having a free end at the separating location.

Abstract: The semiconductor component has several regularly arranged active cells (1), each comprising at least one main defining line (8). A bonding wire (18, 20) is fixed to at least one bonding surface (14, 16) by bonding with a bonding tool, oscillating in a main oscillation direction (22, 24), for external electrical contacting. The bonding surfaces (14, 16) are of such a size and oriented such that the main oscillation direction (22, 24) runs at an angle (?), with a difference of 90° to the main defining line (8).