Abstract: A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.

Abstract: A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.

Abstract: A computer is provided that has a plurality of insertion cards that are interconnected via a bus. One insertion card includes a local processing unit and a first intermediate memory for intermediate storage of messages intended for the local processing unit, and a second intermediate memory for intermediate storage of messages originating from the local processing unit. A third intermediate memory and a fourth intermediate memory are provided for free message locations that are intended for or originate from the local processing unit. The second and the third intermediate memories are each provided with a respective intermediate memory extension in a local memory of the local processing unit.

Abstract: In a computer comprising a plurality of plug-in cards and peripheral plug-in cards interconnected through a bus, plug-in places of the bus are designed as system plug-in places and peripheral plug-in places. A clock line is routed along respective clock jack contacts at the plug-in places and comprises an associated clock plug-in contact on a plug-in card. A universal plug-in card (14) comprises a control plug-in contact (24) which is capable of being connected with a control plug-in jack (22) of the bus (12) and activates a clock output signal of the plug-in card (14) which may be supplied to the bus (12) via the clock plug-in contact (C_LK0). The card (14) is capable of working in a peripheral mode in which a clock plug-in contact (C_LK0) acts as a clock input.

Abstract: In a computer comprising a plurality of plug-in cards and peripheral plug-in cards interconnected through a bus, plug-in places of the bus are designed as system plug-in places and peripheral plug-in places. A clock line is routed along respective clock jack contacts at the plug-in places and comprises an associated clock plug-in contact on a plug-in card. A universal plug-in card (14) comprises a control plug-in contact (24) which is capable of being connected with a control plug-in jack (22) of the bus (12) and activates a clock output signal of the plug-in card (14) which may be supplied to the bus (12) via the clock plug-in contact (C_LK0). The card (14) is capable of working in a peripheral mode in which a clock plug-in contact (C_LK0) acts as a clock input.