Abstract: A method for manufacturing integrated circuits complete with integrated low loss capacitances, inductances, and high Q resistors. Initially a large number of monocrystalline--in their lateral and vertical directions dielectrically insulated--boxes for receiving the active devices of the integrated circuit are generated on a semiconductor substrate wafer with high resistivity. A subset of the completely insulated boxes is to provide for receiving the active devices generated by appropriate bipolar, MOS, or BiCMOS technologies. The other subset is to provide for receiving the passive devices. From these boxes, the monocrystalline semiconductor material is removed completely. In the empty boxes, the walls of which boxes consist of a dielectric, thin film conductor structures are defined by deposition and lithographic processes, eventually forming the passive devices.

Abstract: A method for operation of a radio-controlled clock comprising a quartz-controlled clock synchronized by a time signal receiver with a time signal via a signal processor. In a common array with an additional device, such as a computer or television set, reception of the time signal is generally largely prevented by the interference effect of the additional device. In the method in accordance with the invention, the quartz-controlled clock is therefore synchronized with the time signal solely when the additional device is no longer generating an interference field. For this purpose, a detector is provided that recognizes the operating state of the additional device and permits synchronization of the quartz-controlled clock with the time signal only when the additional device is not generating an interference field, or if so only a reduced one. Furthermore, a radio-controlled clock is described that is suitable for operation by the method in accordance with the invention.

Abstract: In a method of forming an integrated circuit array having a capacitance formed by a pn-junction and separated from other components by a pn-junction, semiconductor areas are provided which connect that zone of the two semiconductor zones forming the pn-junction of the capacitance that extends deeper into the semiconductor element than the other of the two semiconductor zones forming the pn-junction of the capacitance electrically to that zone of the two semiconductor zones forming the separating pn-junction that faces away from the capacitance.

Abstract: In an integrated circuit array having a capacitance formed by a pn-junction and separated from other components by a pn-junction, semiconductor areas are provided which connect that zone of the two semiconductor zones forming the pn-junction of the capacitance that extends deeper into the semiconductor element than the other of the two semiconductor zones forming the pn-junction of the capacitance electrically to that zone of the two semiconductor zones forming the separating pn-junction that faces away from the capacitance.

Abstract: An integrated circuit comprises a semiconductor body with a metal path running at least partially on the component side surface of the semiconductor body itself.The invention also includes the method of making the arrangement.

Abstract: An integrated circuit arrangement comprises a semiconductor body carrying an integrated circuit which is embedded in an insulating material casing together with a plurality of flat strip lines for making electrical connection with the semiconductor body, and a layer of electrically conductive material in or on the casing in a plane substantially parallel to the flat strip lines only on the side of the semiconductor body in which the construction elements forming the integrated circuit are located.

Abstract: A junction type field effect transistor comprises a source region and a drain region extending into a semiconductor body further than the channel region and a gate region located entirely within the channel region between the source and drain regions, leaving an exposed external surface. The invention also includes a method of making such a transistor.

Abstract: A method of producing a semiconductor arrangement comprises diffusing through a diffusion mask into a semiconductor body a semiconductor region of a first type of conductivity and applying to the semiconductor body a semiconductor region of a second type of conductivity extending to the surface of the semiconductor body at least partially in a region which is caused by the diffusion mask when diffusing the region of the first type of conductivity.

Abstract: An improved transistor, such as a control transistor, of the type having a plurality of strip-like emitter regions formed in a single base region in a semiconductor body. The strip-like emitter regions are of different widths and preferably are positioned in spaced side by side relationship and decrease in width in the direction of succession of the strips.