Abstract: A device and a method including current measurement and/or amplification is disclosed. One embodiment provides supplying a current to be measured to a current amplifier. The current is amplified by the current amplifier. The amplified current or a current generated is fed back therefrom to the current amplifier. The current amplifier may include a current mirror. Furthermore, at least one delay means may be used by which the process of current amplification and/or current feedback may be delayed correspondingly.

Abstract: A device and a method including current measurement and/or amplification is disclosed. One embodiment provides supplying a current to be measured to a current amplifier. The current is amplified by the current amplifier. The amplified current or a current generated is fed back therefrom to the current amplifier. The current amplifier may include a current mirror. Furthermore, at least one delay means may be used by which the process of current amplification and/or current feedback may be delayed correspondingly.

Abstract: An integrated circuit is provided. The integrated circuit includes a delay locked loop comprising a binary phase detector which generates a binary phase detector signal, and a decimator receiving the binary phase detector signal, wherein the decimator generates the phase difference signal.

Abstract: A phase-locked loop for adjusting a phase difference between an output signal and an input signal, comprising a phase detector for generating a phase difference signal depending on a phase difference between said output signal and a phase-shifted input signal, a calculator for calculating a signal depending on said phase difference signal and an adjustable offset signal, an oscillator for generating said output signal having an oscillation frequency which is adjusted in response to said calculated signal, and a phase shifter for shifting a signal phase of said input signal by a predetermined phase in response to a control signal to generate said phase-shifted input signal applied to said phase detector.

Abstract: A phase locked loop for recovering a clock signal from a data signal including a delay locked loop with a nonlinear digital phase detector. The delay locked loop that is embedded in the phase locked loop acts like a linear phase detector. The phase locked loop of the present invention can be produced at low cost and is particularly suitable for use in data communication.

Abstract: A phase locked loop for recovering a clock signal from a data signal including a delay locked loop with a nonlinear digital phase detector. The delay locked loop that is embedded in the phase locked loop acts like a linear phase detector. The phase locked loop of the present invention can be produced at low cost and is particularly suitable for use in data communication.

Abstract: A frequency doubling circuit includes an exclusive OR gate which is supplied with an input signal and also with an integrated and quantized version of the input signal. The exclusive OR gate provides an output signal having twice the frequency of the input signal. A weighted adder is provided between an integrator and a quantizer of the frequency doubling circuit. The weighted adder adds the weighted input signal to the integrated signal. Despite runtime effects in the quantizer, the output signal has an undistorted impulse-pause ratio of 1 to 1. The frequency doubling circuit thereby maintains the phase position of the input signal, so that it is suitable for data bus applications with high clock rates or high data rates.

Abstract: In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided by the same division factor. The frequencies of the two frequency-divided signals are then determined by counting processes and are compared by a subtractor. The frequency difference that is determined is then converted into an analog output signal for controlling the clock signal frequency. This method can be applied in the transmission of data.

Abstract: In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided by the same division factor. The frequencies of the two frequency-divided signals are then determined counting processes and are compared by a subtractor. The frequency difference that is determined is then converted into an analog output signal for controlling the clock signal frequency. This method can be applied in the transmission of data.

Abstract: A monolithically integrated oscillator is implemented as ring oscillator with a line driver and a double line formed on one and the same chip. A running time of the double line is selected optimally long and a delay time of the line driver is selected optimally short. The double line can be loaded with controllable capacitors.