Abstract: A method of manufacturing a semiconductor device is set forth, comprising a silicon body (1) having a surface (4) where there are situated a number of semiconductor regions (5, 6) and field oxide regions (7). The semiconductor regions is formed, after the field oxide regions have been provided, by implantations of n-type and p-type dopants. In accordance with the invention the implantations with the n-type dopant (10, 11, 14), which are performed using an implantation mask (8) provided on the surface and comprising openings (9) at the area of a part of the semiconductor regions (5) to be formed, are combined with the implantations with the p-type dopant (12, 13, 15) which are carried out without using the implantation mask. Thus, the semiconductor regions (5, 6) are realised by means of a single implantation mask (8).

Abstract: The invention relates to an integrated circuit connected via a first connection conductor (61) to a first contact area. Between the first connection conductor (61) and a second connection conductor (63), a protection element (8) is connected, which protects the circuit especially from electrostatic discharges. The protection element (8) comprises an active zone (81), which is covered with metal silicide (15) and forms a pn junction (86) with the adjoining part (83) of the semiconductor body (10). On the metal silicide (15), the active zone (81) is provided with an electrode (16), through which the zone (81) is connected to the first connection conductor (61). The use of metal silicide in the integrated circuit in itself has great advantages, but in the protection element the metal silicide layer is found to give rise to a considerably lower reliability. The invention has for its object to obviate this disadvantage without it being necessary to modify the manufacturing process.

Abstract: A method of manufacturing a semiconductor device, in which a depression (1,2,3) in a surface (4) of a semiconductor substrate (5) is filled by covering it with a preplanarized filling layer (8,19,22) and a further planarization layer (9), after which the substrate (5) is brought into contact with an etchant, in which both layers (8,19,22) and (9) are etched at substantially the same rate. According to the invention, the preplanarized filling layer (8,19,22) is formed by covering the surface (4) with a layer of filling material (6) and then removing it beside the depression (1,2,3) over part of its thickness. Thus, the depression (1,2,3) is filled homogeneously in a comparatively simple manner with material of the filling layer (6).

Abstract: A method is provided in which an implantation treatment is carried out at a high energy of implantation in a semiconductor body (1) provided with a pattern of field insulation (6a) and in which the semiconductor body is provided with a masking, comprising a comparatively thin layer (8), a second comparatively thick layer (9) of a semi-masking material and a third comparatively thin layer (10). The second layer (9) is provided with openings (12) and the first layer (8) covers at least those parts of the surface which correspond to these openings (12). The third layer (10) has openings (22) each corresponding to one of the openings (12). The material of the first layer (8) differs from that of the second layer (9) and the material of the second layer (9) differs from that of the third layer (10). Preferably, simultaneously with the second layer (9) on the front side a semiconductor layer (19) is provided on the back side (3 ) of the semiconductor body (1).