Patents by Inventor Rejeev K. Nalawadi

Rejeev K. Nalawadi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6704840
    Abstract: A computer system and method for computer initialization with caching includes enabling at least one cache memory and then copying an option basic input/output system (BIOS) from a first memory to a Programmable Attribute Map (PAM) main memory area, the copying including executing a cache-line fill to the at least one cache memory. Initialization is then performed by providing control to the option BIOS, the execution being performed substantially from the at least one cache memory. Processor Memory Type Range Registers (MTRRs) for the PAM memory area may be programmed as write-back. The at least one cache memory may be at least one of level 1 (L1) and level 2 (L2) processor cache memories. The first memory may be a flash memory or a ROM Read Only Memory (ROM). The at least one cache memory may be flushed upon completion of the option BIOS execution.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: March 9, 2004
    Assignee: Intel Corporation
    Inventors: Rejeev K. Nalawadi, Faraz A. Siddiqi