Patents by Inventor Reji K. Koshy

Reji K. Koshy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming MOS transistors with improved sidewall structures
    Patent number: 7078347
    Abstract: A gate structure (30) is formed over a semiconductor (10). Sidewall structures (200) of a first width W1 are formed adjacent to the gate structure (30) and source and drain regions (90) are formed in the semiconductor (10). An etch process is performed to reduce the width of the sidewall structure to W2 and silicide regions (110) are then formed adjacent to the sidewall structures (205).
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: July 18, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Freidoon Mehrad, Scott F. Johnson, Reji K. Koshy
  • Method for forming MOS transistors with improved sidewall structures
    Publication number: 20040175911
    Abstract: A gate structure (30) is formed over a semiconductor (10). Sidewall structures (200) of a first width W1 are formed adjacent to the gate structure (30) and source and drain regions (90) are formed in the semiconductor (10). An etch process is performed to reduce the width of the sidewall structure to W2 and silicide regions (110) are then formed adjacent to the sidewall structures (205).
    Type: Application
    Filed: March 6, 2003
    Publication date: September 9, 2004
    Inventors: Freidoon Mehrad, Scott F. Johnson, Reji K. Koshy
  • Process for reducing dopant loss for semiconductor devices
    Publication number: 20030129804
    Abstract: A method of forming a semiconductor device includes doping at least one region of an at least partially formed semiconductor device. The method further includes depositing at least one spacer layer outwardly from the at least one region of the at least partially formed semiconductor device. The at least one deposited spacer layer is formed in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the at least partially formed semiconductor device.
    Type: Application
    Filed: May 14, 2002
    Publication date: July 10, 2003
    Inventors: Manoj Mehrotra, Wayne A. Bather, Reji K. Koshy, Amitabh Jain, Mark S. Rodder, Rajesh B. Khamankar, Paul A. Tiner, Rick L. Wise, Darin K. Wedel