Patents by Inventor Remco Van De Beek
Remco Van De Beek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10009070Abstract: A load-modulation detection component for an inductive coupling reader device. The load-modulation receiver device is arranged to receive an antenna voltage signal representative of a voltage across an antenna of the inductive coupling reader device and output at least one load-modulated signal. The load-modulation detection component comprises a down-converter component arranged to mix the antenna voltage signal with a down-conversion signal to generate a down-converted signal, a series capacitive component coupled in series between an output of the down-converter component and an output of the load-modulation receiver, and a switched capacitor resistor circuit coupled between the output of the load-modulation receiver and a first reference voltage.Type: GrantFiled: July 6, 2017Date of Patent: June 26, 2018Assignee: NXP B.V.Inventor: Remco Van De Beek
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Patent number: 9973196Abstract: Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.Type: GrantFiled: March 30, 2016Date of Patent: May 15, 2018Assignee: NXP B.V.Inventors: Jos Verlinden, Remco van de Beek, Stefan Mendel
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Publication number: 20180034512Abstract: A load-modulation detection component for an inductive coupling reader device. The load-modulation receiver device is arranged to receive an antenna voltage signal representative of a voltage across an antenna of the inductive coupling reader device and output at least one load-modulated signal. The load-modulation detection component comprises a down-converter component arranged to mix the antenna voltage signal with a down-conversion signal to generate a down-converted signal, a series capacitive component coupled in series between an output of the down-converter component and an output of the load-modulation receiver, and a switched capacitor resistor circuit coupled between the output of the load-modulation receiver and a first reference voltage.Type: ApplicationFiled: July 6, 2017Publication date: February 1, 2018Inventor: Remco VAN DE BEEK
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Patent number: 9876631Abstract: A digital synchronizer is disclosed with a phase locked loop and a carrier generator. The phase locked loop is configured to produce an output signal having the same frequency as an input signal by selecting a divider ratio of a frequency divider with a control signal, the frequency divider divides the frequency of a high frequency signal by the divider ratio to provide the output signal; carrier generator is configured to generate an oversampled carrier signal by using the control signal to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal.Type: GrantFiled: March 30, 2016Date of Patent: January 23, 2018Assignee: NXP B.V.Inventors: Remco van de Beek, Jos Verlinden, Ghiath Al-kadi
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Patent number: 9798338Abstract: Embodiments of power source circuits and methods for operating a power source circuit are described. In one embodiment, a method for operating a power source circuit involves receiving at the power source circuit at least one digital signal from a feedback loop and increasing or decreasing an output power signal of the power source circuit in response to the at least one digital signal. Other embodiments are also described.Type: GrantFiled: August 4, 2015Date of Patent: October 24, 2017Assignee: NXP B.V.Inventor: Remco Van de Beek
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Patent number: 9705544Abstract: A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analog-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols.Type: GrantFiled: April 22, 2016Date of Patent: July 11, 2017Assignee: NXP B.V.Inventors: Remco van de Beek, Jos Verlinden
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Patent number: 9686041Abstract: An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.Type: GrantFiled: August 31, 2015Date of Patent: June 20, 2017Assignee: NXP B.V.Inventors: Remco van de Beek, Massimo Ciacci, Ghiath Al-kadi
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Publication number: 20160315646Abstract: A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analogue-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols.Type: ApplicationFiled: April 22, 2016Publication date: October 27, 2016Inventors: Remco van de Beek, Jos Verlinden
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Publication number: 20160294398Abstract: Apparatus for clock synchronisation comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.Type: ApplicationFiled: March 30, 2016Publication date: October 6, 2016Inventors: Jos Verlinden, Remco van de Beek, Stefan Mendel
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Publication number: 20160294541Abstract: A digital synchronizer is disclosed, comprising: a phase locked loop (100) configured to produce an output signal (clkFc) having the same frequency as an input signal (Frx) by selecting a divider ratio (/P) of a frequency divider (130) with a control signal (Pctrl), the frequency divider (130) configured to divide the frequency of a high frequency signal (clkHF) by the divider ratio (/P) to provide the output signal (clkFc); a carrier generator (300) comprising a look-up table (320), the carrier generator (300) configured to generate an oversampled carrier signal using the look-up-table (320) by using the control signal (Pctrl) to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal (clkFc).Type: ApplicationFiled: March 30, 2016Publication date: October 6, 2016Inventors: Remco van de Beek, Jos Verlinden, Ghiath Al-kadi
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Patent number: 9379884Abstract: A symbol clock recovery circuit comprising an ADC, a controllable inverter and a timing detector. A timing detector input terminal is configured to receive an ADC output signal from an ADC output terminal; a timing detector output terminal is configured to provide a digital output signal; and a first timing detector feedback terminal is configured to provide a first feedback signal to the inverter control terminal. The timing detector is configured to determine an error signal associated with the received ADC output signal, and set the first feedback signal in accordance with the error signal.Type: GrantFiled: May 1, 2015Date of Patent: June 28, 2016Assignee: NXP B.V.Inventors: Massimo Ciacci, Ghiath Al-kadi, Remco van de Beek
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Publication number: 20160036325Abstract: Embodiments of power source circuits and methods for operating a power source circuit are described. In one embodiment, a method for operating a power source circuit involves receiving at the power source circuit at least one digital signal from a feedback loop and increasing or decreasing an output power signal of the power source circuit in response to the at least one digital signal. Other embodiments are also described.Type: ApplicationFiled: August 4, 2015Publication date: February 4, 2016Inventor: Remco Van de Beek
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Publication number: 20150372787Abstract: An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Inventors: Remco van de Beek, Massimo Ciacci, Ghiath Al-kadi
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Publication number: 20150318979Abstract: A symbol clock recovery circuit comprising an ADC, a controllable inverter and a timing detector. A timing detector input terminal is configured to receive an ADC output signal from an ADC output terminal; a timing detector output terminal is configured to provide a digital output signal; and a first timing detector feedback terminal is configured to provide a first feedback signal to the inverter control terminal. The timing detector is configured to determine an error signal associated with the received ADC output signal, and set the first feedback signal in accordance with the error signal.Type: ApplicationFiled: May 1, 2015Publication date: November 5, 2015Inventors: Massimo Ciacci, Ghiath Al-kadi, Remco van de Beek
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Patent number: 9172329Abstract: Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.Type: GrantFiled: August 1, 2012Date of Patent: October 27, 2015Assignee: NXP B.V.Inventors: Massimo Ciacci, Jos Verlinden, Remco van de Beek
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Patent number: 9124393Abstract: An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.Type: GrantFiled: December 20, 2013Date of Patent: September 1, 2015Assignee: NXP B.V.Inventors: Remco van de Beek, Massimo Ciacci, Ghiath Al-kadi
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Publication number: 20150180608Abstract: An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Inventors: Remco van de Beek, Massimo Ciacci, Ghiath Al-kadi
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Patent number: 8928401Abstract: Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.Type: GrantFiled: November 26, 2012Date of Patent: January 6, 2015Assignee: NXP, B.V.Inventors: Jos Verlinden, Remco van de Beek, Massimo Ciacci
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Publication number: 20140145787Abstract: Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: NXP B.V.Inventors: Jos Verlinden, Remco van de Beek, Massimo Ciacci
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Publication number: 20140038534Abstract: Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.Type: ApplicationFiled: August 1, 2012Publication date: February 6, 2014Inventors: Massimo Ciacci, Jos Verlinden, Remco van de Beek