Abstract: A power semiconductor module includes an insulating substrate with a top metallization layer; a semiconductor chip bonded to the top metallization layer; and a terminal welded with a foot to the top metallization layer and electrically interconnected to the semiconductor chip. At least one of the top metallization layer and a bottom metallization layer of the substrate provided opposite to the top metallization layer comprises a plurality of dimples, which are distributed in a connection region below and/or around the welded foot.

Abstract: A power semiconductor module includes an insulating substrate with a top metallization layer; a semiconductor chip bonded to the top metallization layer; and a terminal welded with a foot to the top metallization layer and electrically interconnected to the semiconductor chip. At least one of the top metallization layer and a bottom metallization layer of the substrate provided opposite to the top metallization layer comprises a plurality of dimples, which are distributed in a connection region below and/or around the welded foot.

Abstract: The present application relates to a method of generating a power semiconductor module including a carrier layer and a substrate having a terminal connection area, the method comprising: soldering the substrate to the carrier layer by forming a solder layer; wherein the solder layer is formed such, that a pre-defined cavity is provided in the solder layer adjacent to the substrate and located opposite to the terminal connection area; and welding a terminal to the terminal connection area of the substrate. The present application provides a method of generating a power semiconductor module which is especially cost-saving to perform and allows a reliable generation of high quality modules.